參數(shù)資料
型號(hào): M38867E8AFS
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 10 MHz, MICROCONTROLLER, CQCC80
封裝: CERAMIC, LCC-80
文件頁(yè)數(shù): 372/379頁(yè)
文件大?。?/td> 4123K
代理商: M38867E8AFS
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HARDWARE
1-68
3886 Group User’s Manual
FLASH MEMORY MODE
The M38869FFAHP/GP has the flash memory mode in addition to
the normal operation mode (microcomputer mode). The user can
use this mode to perform read, program, and erase operations for
the internal flash memory.
The M38869FFAHP/GP has three modes the user can choose:
the parallel input/output and serial input/output mode, where the
flash memory is handled by using the external programmer, and
the CPU reprogramming mode, where the flash memory is
handled by the central processing unit (CPU). The following ex-
plains these modes.
(1) Flash memory mode 1 (parallel I/O mode)
The parallel I/O mode can be selected by connecting wires as
shown in Figures 68 and supplying power to the VCC and VPP
pins. In this mode, the M38869FFAHP/GP operates as an equiva-
lent of MITSUBISHI’s CMOS flash memory M5M28F101.
However, because the M38869FFAHP/GP’s internal memory has
a capacity of 60 Kbytes, programming is available for addresses
0100016 to 0FFFF16, and make sure that the data in addresses
0000016 to 00FFF16 and addresses 1000016 to 1FFFF16 are FF16.
Note also that the M38869FFAHP/GP does not contain a facility to
read out a device identification code by applying a high voltage to
address input (A9). Be careful not to erratically set program condi-
tions when using a general-purpose PROM programmer.
Table 20 shows the pin assignments when operating in the paral-
lel input/output mode.
Table 20
Pin assignments of M38869FFAHP/GP when
operating in the parallel input/output mode
VCC
VPP
VSS
Address input
Data I/O
__
CE
___
OE
___
WE
M38869FFAHP/GP
VCC
CNVSS
VSS
Ports P0, P1, P31
Port P2
P36
P37
P33
M5M28F101
VCC
VPP
VSS
A0–A16
D0–D7
__
CE
__
OE
___
WE
Functional Outline (parallel input/output mode)
In the parallel input/output mode, the M38869FFAHP/GP allow the
user to choose an operation mode between the read-only mode
and the read/write mode (software command control mode) de-
pending on the voltage applied to the VPP pin. When VPP = VPPL,
the read-only mode is selected, and the user can choose one of
three states (e.g., read, output disable, or standby) depending on
___ ___
___
inputs to the CE, OE, and WE pins. When VPP = VPPH, the read/
write mode is selected, and the user can choose one of four states
(e.g., read, output disable, standby, or write) depending on inputs
__
___
to the CE, OE, and WE pins. Table 21 shows assignment states of
control input and each state.
q Read
__
The microcomputer enters the read state by driving the CE, and
__
___
OE pins low and the WE pin high; and the contents of memory
corresponding to the address to be input to address input pins
(A0–A16) are output to the data input/output pins (D0–D7).
q Output disable
The microcomputer enters the output disable state by driving the
__
___
__
CE pin low and the WE and OE pins high; and the data input/out-
put pins enter the floating state.
q Standby
__
The microcomputer enters the standby state by driving the CE pin
high. The M38869FFAHP/GP is placed in a power-down state
consuming only a minimal supply current. At this time, the data in-
put/output pins enter the floating state.
q Write
The microcomputer enters the write state by driving the VPP pin
___
__
high (VPP = VPPH) and then the WE pin low when the CE pin is
__
low and the OE pin is high. In this state, software commands can
be input from the data input/output pins, and the user can choose
program or erase operation depending on the contents of this soft-
ware command.
Pin
Mode
Read
Output disable
Standby
Read
Output disable
Standby
Write
Read-only
Read/Write
__
CE
VIL
VIH
VIL
VIH
VIL
VIH
×
VIL
VIH
×
VIH
Table 21 Assignment sates of control input and each state
__
OE
___
WE
VIH
×
VIH
×
VIL
VPPL
VPPH
VPP
Output
Floating
Output
Floating
Input
Data I/O
Note:
× can be VIL or VIH.
State
FUNCTIONAL DESCRIPTION
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