參數(shù)資料
型號(hào): M38503M2H-XXXFP
廠(chǎng)商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù): 48/99頁(yè)
文件大?。?/td> 1384K
代理商: M38503M2H-XXXFP
48
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H/A)
CLOCK GENERATING CIRCUIT
The 3850 group (spec. H/A) has two built-in oscillation circuits. An
oscillation circuit can be formed by connecting a resonator be-
tween X
IN
and X
OUT
(X
CIN
and X
COUT
). Use the circuit constants
in accordance with the resonator manufacturer
s recommended
values. No external resistor is needed between X
IN
and X
OUT
since a feed-back resistor exists on-chip. However, an external
feed-back resistor is needed between X
CIN
and X
COUT
.
Immediately after power on, only the X
IN
oscillation circuit starts
oscillating, and X
CIN
and X
COUT
pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal clock
φ
is the frequency of X
IN
divided by 8. After re-
set is released, this mode is selected.
(2) High-speed mode
The internal clock
φ
is half the frequency of X
IN
.
(3) Low-speed mode
The internal clock
φ
is half the frequency of X
CIN
.
I
Note
If you switch the mode between middle/high-speed and low-
speed, stabilize both X
IN
and X
CIN
oscillations. The sufficient time
is required for the sub-clock to stabilize, especially immediately af-
ter power on and at returning from the stop mode. When switching
the mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(X
IN
) > 3
f(X
CIN
).
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock X
IN
in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to
1.
When the main clock X
IN
is
restarted (by setting the main clock stop bit to
0
), set sufficient
time for oscillation to stabilize.
The sub-clock X
CIN
-X
COUT
oscillating circuit can not directly input
clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock
φ
stops at an
H
level, and X
IN
and X
CIN
oscillation stops. When the oscillation
stabilizing time set after STP instruction released bit is
0,
the
prescaler 12 is set to
FF
16
and timer 1 is set to
01
16
.
When the
oscillation stabilizing time set after STP instruction released bit is
1,
set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1.
Either X
IN
or X
CIN
divided by 16 is input to the prescaler 12 as
count source. Oscillator restarts when an external interrupt is re-
ceived, but the internal clock
φ
is not supplied to the CPU (remains
at
H
) until timer 1 underflows. The internal clock
φ
is supplied for
the first time, when timer 1 underflows. This ensures time for the
clock oscillation using the ceramic resonators to be stabilized.
When the oscillator is restarted by reset, apply
L
level to the
RESET pin until the oscillation is stable since a wait time will not
be generated.
Fig. 52 Ceramic resonator circuit
Fig. 53 External clock input circuit
(2) Wait mode
If the WIT instruction is executed, the internal clock
φ
stops at an
H
level, but the oscillator does not stop. The internal clock
φ
re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to
1
before ex-
ecuting of the STP or WIT instruction.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock X
IN
divided by 16. Accordingly, set the
timer 1 interrupt enable bit to
0
before executing the STP instruc-
tion.
I
Note
When using the oscillation stabilizing time set after STP instruction
released bit set to
1
, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
X
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f
R
d
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