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參數(shù)資料
| 型號(hào)： | M38503M2-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-42 |
| 文件頁(yè)數(shù)： | 255/285頁(yè) |
| 文件大?。?/td> | 2992K |
| 代理商： | M38503M2-XXXSP |
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HARDWARE
3850 Group (Spec. H) User’s Manual
FUNCTIONAL DESCRIPTION
1-53
Fig. 54 Block erase flowchart
Program Command (4016)
The program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
Whether the write operation is completed can be confirmed by read-
_____
ing the status register or the RY/BY signal status. When the program
starts, the read status register mode is accessed automatically and
the content of the status register can be read out from the data bus
(D0–D7). The status register bit 7 (SR7) is set to “0” at the same time
the write operation starts and is returned to “1” upon completion of
the write operation. In this case, the read status register mode re-
mains active until the read array command (FF16) is written.
____
The RY/BY pin is “L” during write operation and “H” when the write
operation is completed as is the status register bit 7.
At program end, program results can be checked by reading the sta-
tus register.
Erase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that fol-
lows, the system starts erase all blocks( erase and erase verify).
Whether the erase all blocks command is terminated can be con-
____
firmed by reading the status register or the RY/BY signal status .
When the erase all blocks operation starts, the read status register
mode is accessed automatically and the content of the status regis-
ter can be read out. The status register bit 7 (SR7) is set to “0” at the
same time the erase operation starts and is returned to “1” upon
completion of the erase operation. In this case, the read status regis-
ter mode remains active until the read array command (FF16) is writ-
ten.
____
The RY/BY pin is “L” during erase operation and “H” when the erase
operation is completed as is the status register bit 7.
At erase all blocks end, erase results can be checked by reading the
status register. For details, refer to the section where the status reg-
ister is detailed.
Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” in the second bus cycle that
follows to the block address of a flash memory block, the system
initiates a block erase (erase and erase verify) operation.
Whether the block erase operation is completed can be confirmed
____
by reading the status register or the RY/BY signal. At the same time
the block erase operation starts, the read status register mode is
automatically entered, so the content of the status register can be
read out. The status register bit 7 (SR7) is set to “0” at the same time
the block erase operation starts and is returned to “1” upon comple-
tion of the block erase operation. In this case, the read status regis-
ter mode remains active until the read array command (FF16) is writ-
ten.
____
block erase operation is completed as is the status register bit 7.
After the block erase operation is completed, the status register can
be read out to know the result of the block erase operation. For de-
tails, refer to the section where the status register is detailed.
Fig. 53 Page program flowchart
Start
Write 4016
Status register
read
Program completed
(Read command
FF16 write)
NO
YES
Write address
Write data
SR4=0?
Program
error
NO
YES
SR7=1?
or
RY/BY=1?
Write
Write 2016
2016/D016
Block address
Erase completed
(Read command
FF16 write)
NO
YES
Start
Write
SR5=0?
Erase error
YES
NO
2016:Erase all blocks
D016:Block erase
SR7=1?
or
RY/BY=1?
Status register
read
相關(guān)PDF資料 |
PDF描述 |
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| M38503M4-XXXSP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
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| M38510/00107BCX | TTL/H/L SERIES, QUAD 2-INPUT NAND GATE, CDIP14 |
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