44
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Fig. 50 Initial status at reset
Address
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 output control register
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
Key input control register
PULL register A
PULL register B
Serial I/O1 status register
Serial I/O1 control register
UART control register
Serial I/O2 control register
Timer X (low-order)
Timer X (high-order)
Timer Y (low-order)
Timer Y (high-order)
Timer 1
Timer 2
Timer 3
Timer X mode register
Timer Y mode register
Timer 123 mode register
T
OUT
/
φ
output control register
PWM control register
0001
16
0003
16
0005
16
0007
16
0009
16
000B
16
000D
16
000F
16
0015
16
0016
16
0017
16
0019
16
001A
16
001B
16
001D
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
Register contents
Address
Note:
The contents of all other register and RAM are undefined after reset, so they must be initialized by software.
: Undefined
Register contents
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
3F
16
00
16
00
16
16
FF
16
FF
16
FF
16
FF
16
FF
16
01
16
FF
16
00
16
00
16
00
16
00
16
00
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
(PS)
(PC
H
)
(PC
L
)
A-D control register
A-D conversion register
(low-order)
A-D conversion register
(high-order)
D-A1 conversion register
D-A2 conversion register
D-A control register
Watchdog timer control register
Segment output enable register
LCD mode register
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Processor status register
Program counter
Watchdog timer (high-order)
Watchdog timer (low-order)
Contents of address FFFD
16
Contents of address FFFC
16
08
16
XX
16
XX
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
3F
16
FF
16
1
1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0
0 0 1 1 1 1 1 1
0 1 0 0 1 0 0 0