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Rev.1.01
Aug 22, 2003
page 5 of 69
3826 Group (A version)
Table 2 Pin description (2)
Function
Pin
Name
Function except a port function
P40
P41/INT1,
P42/INT2
P43/φ/TOUT
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
P50/PWM0,
P51/PWM1
P52/RTP0,
P53/RTP1
P54/CNTR0,
P55/CNTR1
P56/DA1
P57/ADT/DA2
P60/SIN2/AN0,
P61/SOUT2/AN1,
P62/SCLK21/AN2,
P63/SCLK22/AN3
P64/AN4–
P67/AN7
P70/INT0
P71–P77
I/O port P4
I/O port P5
I/O port P6
Input port P7
I/O port P7
Sub-clock output
Sub-clock input
1-bit I/O port.
CMOS compatible input level.
N-channel open-drain output structure.
I/O direction register allows this pin to be individually programmed as either input or output.
7-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
Pull-up control is enabled.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
Pull-up control is enabled.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
Pull-up control is enabled.
1-bit input port.
INTi interrupt input pins
System clock φ output pin
Timer 2 output pin
Serial I/O1 I/O pins
PWM output pins
Real time port output pins
Timer X, Y I/O pins
D-A converter output pin
A-D external trigger input pin
A-D converter input pins
Serial I/O2 I/O pins
A-D converter input pins
XCOUT
XCIN
INT0 interrupt input pin
7-bit I/O port.
CMOS compatible input level.
N-channel open-drain output structure.
I/O direction register allows each pin to be individually programmed as either input or output.
Sub-clock generating circuit I/O pins.
(Connect a oscillator. External clock cannot be used.)