參數(shù)資料
型號(hào): M38257M8DXXXFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù): 24/339頁(yè)
文件大?。?/td> 3175K
代理商: M38257M8DXXXFP
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3825 GROUP USER’S MANUAL
List of figures
iii
Fig. 2.3.27 Example of setting registers for using timer mode ........................................................ 2-70
Fig. 2.3.28 Example of setting registers for using period measurement mode ............................... 2-71
Fig. 2.3.29 Example of setting registers for using event counter mode ........................................... 2-72
Fig. 2.3.30 Example of setting registers for using pulse width HL continuously measurement mode .......................... 2-73
Fig. 2.3.31 Example of peripheral circuit ......................................................................................... 2-74
Fig. 2.3.32 Connection of timer and setting of division ratio ............................................................ 2-74
Fig. 2.3.33 Setting of related registers ............................................................................................. 2-75
Fig. 2.3.34 Control procedure .......................................................................................................... 2-75
Fig. 2.3.35 Example of peripheral circuit ......................................................................................... 2-76
Fig. 2.3.36 Setting of related registers ............................................................................................. 2-76
Fig. 2.3.37 Ringer signal waveform ................................................................................................. 2-77
Fig. 2.3.38 Operation timing when ringing pulse is input ................................................................. 2-77
Fig. 2.3.39 Control procedure .......................................................................................................... 2-78
Fig. 2.3.40 Application connection example when RTP is used ...................................................... 2-79
Fig. 2.3.41 RTP output example ...................................................................................................... 2-80
Fig. 2.3.42 Timer X interrupt processing procedure example when RTP is used ........................... 2-80
Fig. 2.4.1 Timer mode operation example ....................................................................................... 2-85
Fig. 2.4.2 Rewriting example of counter and latch corresponding to timers 1 or 3 .......................... 2-86
Fig. 2.4.3 Rewriting example of timer 2 counter and timer 2 latch (Writing in timer 2 latch only) .... 2-87
Fig. 2.4.4 Pulse output example ...................................................................................................... 2-88
Fig. 2.4.5 Memory allocation of timer-related registers ................................................................... 2-89
Fig. 2.4.6 Structure of latches .......................................................................................................... 2-90
Fig. 2.4.7 Structure of timer counters .............................................................................................. 2-91
Fig. 2.4.8 Structure of timer 123 mode register ............................................................................... 2-92
Fig. 2.4.9 Structure of interrupt request register 1 ........................................................................... 2-94
Fig. 2.4.10 Structure of interrupt request register 2 ......................................................................... 2-95
Fig. 2.4.11 Structure of interrupt control register 1 .......................................................................... 2-96
Fig. 2.4.12 Structure of interrupt control register 2 .......................................................................... 2-97
Fig. 2.4.13 Example of setting registers for timers 1, 2, and 3 ........................................................ 2-98
Fig. 2.4.14 Setting of related registers ............................................................................................. 2-99
Fig. 2.4.15 Control procedure ........................................................................................................ 2-100
Fig. 2.5.1 External connection example in clock synchronous mode ............................................ 2-102
Fig. 2.5.2 Shift clock ...................................................................................................................... 2-103
Fig. 2.5.3 Transmit operation in clock synchronous mode ............................................................ 2-106
Fig. 2.5.4 Transmit timing example in clock synchronous mode ................................................... 2-107
Fig. 2.5.5 Receive operation in clock synchronous mode ............................................................. 2-109
Fig. 2.5.6 Receive timing example in clock synchronous mode .................................................... 2-109
Fig. 2.5.7 Transmit/receive timing example in clock synchronous mode ...................................... 2-110
Fig. 2.5.8 External connection example in UART mode ................................................................ 2-111
Fig. 2.5.9 Transfer data format in UART mode ............................................................................. 2-113
Fig. 2.5.10 All transfer data formats in UART mode ...................................................................... 2-114
Fig. 2.5.11 Transmit timing example in UART mode ..................................................................... 2-116
Fig. 2.5.12 Receive timing example in UART mode ...................................................................... 2-118
Fig. 2.5.13 Memory allocation of serial I/O-related registers ......................................................... 2-120
Fig. 2.5.14 Structure of transmit/receive buffer register ................................................................ 2-120
Fig. 2.5.15 Structure of serial I/O status register ........................................................................... 2-121
Fig. 2.5.16 Structure of serial I/O control register .......................................................................... 2-123
Fig. 2.5.17 Structure of UART control register .............................................................................. 2-126
Fig. 2.5.18 Transmitting method in clock synchronous mode (1) .................................................. 2-128
Fig. 2.5.19 Transmitting method in clock synchronous mode (2) .................................................. 2-129
Fig. 2.5.20 Receiving method in clock synchronous mode (1) ...................................................... 2-130
Fig. 2.5.21 Receiving method in clock synchronous mode (2) ...................................................... 2-131
Fig. 2.5.22 Transmitting method in UART mode (1) ...................................................................... 2-132
Fig. 2.5.23 Transmitting method in UART mode (2) ...................................................................... 2-133
Fig. 2.5.24 Receiving method in UART mode (1) .......................................................................... 2-134
Fig. 2.5.25 Receiving method in UART mode (2) .......................................................................... 2-135
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