Page
Corrections and Supplementary Explanation for “3822 Group User’s Manuals” No.2
M380-17-9910
(3/5)
Rev.
Contents
Previous change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before setting below, clear the interrupt enable bits
(timer X or CNTR0) and the interrupt request bits (timer
X or CNTR0) to “0”.
After setting below, set the interrupt enable bits (timer
X or CNTR0) to “1” (interrupts enabled).
After change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before timer X stops counting (before setting below),
clear the interrupt enable bit (timer X or CNTR 0) to “0”.
After setting below, clear the interrupt request bit (timer
X or CNTR0) to “0” and next set the interrupt enable bit
(timer X or CNTR0) to “1” (interrupt enabled).
Set last.
Previous change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before setting below, clear the interrupt enable bits
(timer X or CNTR0) and the interrupt request bits (timer
X or CNTR0) to “0”.
After setting below, set the interrupt enable bits (timer
X or CNTR0) to “1” (interrupts enabled).
After change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before timer X stops counting (before setting below),
clear the interrupt enable bit (timer X or CNTR 0) to “0”.
After setting below, clear the interrupt request bit (timer
X or CNTR0) to “0” and next set the interrupt enable bit
(timer X or CNTR0) to “1” (interrupt enabled).
Set last.
Previous change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before setting below, clear the timer Y interrupt enable
bit and the timer Y interrupt request bit to “0”.
After setting below, set the timer Y interrupt enable bit
to “1” (interrupts enabled).
After change
[Notes on use]
Notes 1: For using interrupt processing, set the following:
Before timer Y stops counting (before setting below),
clear the timer Y interrupt enable bit to “0”.
After setting below, clear the timer Y interrupt request
bit to “0” and next set the timer Y interrupt enable bit to
“1” (interrupt enabled).
Set last.
P2-67
(1) Timer X
s Event counter mode
Fig. 2.3.24
P2-68
(1) Timer X
s Pulse width measurement
mode
Fig. 2.3.25
P2-70
(2) Timer Y
s Timer mode
Fig. 2.3.27
B