參數(shù)資料
型號: M38220MCMFS
廠商: Mitsubishi Electric Corporation
元件分類: FPGA
英文描述: 50000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 75/78頁
文件大?。?/td> 998K
代理商: M38220MCMFS
REVISION HISTORY
3822 GROUP DATA SHEET
Rev.
Date
Description
Page
Summary
(1/2)
1.0
01/20/98
First Edition
2.0
10/23/00
1
2
3
4
5
6
7
8
9
10
11–13
11
12
13
15
17
18
21
22
24
25
26
29
30
32
33
34
“qMemory size” of “FEATURES” is partly revised.
“qSerial I/O” of “FEATURES” is partly revised.
“qA-D converter” of “FEATURES” is added.
“q2 clock generating circuits” of “FEATURES” is partly revised.
“qPower source voltage” of “FEATURES” is partly revised.
“qPower dissipation” of “FEATURES” is partly added.
Product name into Figure 1 is revised.
Product name into Figure 2 is revised.
Figure 3 is partly revised.
“Function” of “Vcc, Vss” into Table 1 is partly revised.
“Function except a port function” into Table 2 is partly revised.
Figure 4 is partly revised.
Explanations of “GROUP EXPANSION (STANDARD, ONE TIME PROM VER-
SION, EPROM VERSION)” are partly revised.
Figure 5 is partly revised.
Table 3 is partly revised.
Explanations of “GROUP EXPANSION (EXTENDED OPERATING TEMPERA-
TURE VERSION)” are partly revised.
Figure 6 is partly revised.
Table 4 is partly revised.
“GROUP EXPANSION (M VERSION)” is added.
Figure 7 is added.
Table 5 is added.
“GROUP EXPANSION (H VERSION)” is added.
Figure 8 is added.
Table 6 is added.
Explanations of “CENTRAL PROCESSING UNIT (CPU)” are added.
Figure 9 is added.
Figure 10 is added.
Table 7 is added.
Table 8 is added.
Figure 12 is partly revised.
Figure 14 is partly revised.
Table 9 is partly revised.
Figure 17 is partly revised.
Explanations of “Interrupt Control” is partly added.
Explanations of “Interrupt Operation” is partly revised.
Explanations of “sNotes” are partly revised.
Table 9 is partly revised.
Explanations of “Key Input Interrupt (Key-on wake up)” are partly revised.
Figure 21 is partly revised.
Explanations of “qTimer X write control” are partly revised.
Explanations of “qReal time port control” are partly revised.
Figure 25 is partly revised.
Figure 27 is partly revised.
Figure 29 is partly revised.
Explanations of “[Channel Selector]” are partly added.
Explanations of “[Comparator and Control Circuit]” are partly added.
Figure 32 is partly revised.
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