參數(shù)資料
型號(hào): M38199MF-XXXKP
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, MICROCONTROLLER, PQFP100
封裝: 100P6P-E
文件頁(yè)數(shù): 151/217頁(yè)
文件大?。?/td> 2564K
代理商: M38199MF-XXXKP
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26
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(1) Serial I/O Ordinary Mode
Either an internal clock or an external clock can be selected
as the synchronous clock for serial I/O transfer. A dedicated
divider is built in as the internal clock for selecting of 6 clocks.
If internal clock is selected, transfer starts with a write signal
to a serial I/O register (addresses 001B16, 001F16, or
002616). After 8 bits have been transferred, the SOUT pin goes
to high impedance state.
If external clock is selected, control the clock externally be-
cause the contents of the serial I/O register continue to shift
during inputting the transfer clock. In this case, note that the
SOUT pin does not go to high impedance state at the comple-
tion of data transfer.
The interrupt request bit is set at the completion of the trans-
fer of 8 bits, regardless of whether the internal or external
clock is selected.
Fig. 15 Serial I/O timing in the serial I/O ordinary mode (for LSB first)
(2) Serial I/O Automatic Transfer Mode
The serial I/O1 has the automatic transfer function. For auto-
matic transfer, switch to the automatic transfer mode by
setting the serial I/O automatic transfer control register (ad-
dress 001A16).
The following memory spaces and registers used to enable
automatic transfer mode:
32-byte serial I/O automatic transfer RAM
A serial I/O automatic transfer control register
A serial I/O automatic transfer interval register
A serial I/O automatic transfer data pointer
When using serial I/O automatic transfer, set the serial I/O1
control register (address 001916) in the same way as the se-
rial I/O ordinary mode. However, note that when external
clock is selected, port P67 becomes the CS input pin by set-
ting the bit 4 (the SRDY1 output selection bit ) of the serial I/O1
control register to “1”.
Serial I/O Automatic Transfer Control Register
(SIOAC) 001A16
The serial I/O automatic transfer control register (address 001A16)
consists of 4 bits which control automatic transfer.
Fig. 16 Structure of serial I/O automatic transfer control register
D1
Synchronous
clock
Interrupt request bit set
If internal clock is selected, the SOUT pin goes to high impedance state
at the completion of data transfer.
Note :
D0
D2
D3
D4
D5
D6
D7
(Note)
Transfer clock
Serial I/O register
write signal
Serial I/O output
SOUT
Serial I/O input
SIN
Receive enable
signal
SRDY
Automatic transfer control bit
0 : Serial I/O ordinary mode
(serial I/O1 interrupt)
1 : Automatic transfer mode
(serial I/O1 automatic transfer interrupt)
Automatic transfer start bit
0 : Transfer completion
1 : Transferring(starts by writing “1”)
Transfer mode switch bit
0 : Fullduplex(transmit and receive)
mode
1 : Transmit-only mode
Synchronous clock output
pin selection bit
0 : SCLK11
1 : SCLK12
Not used (return “0” when read)
b7
Serial I/O automatic transfer control register
(SIOAC : address 001A16)
b0
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