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參數(shù)資料
| 型號： | M38198MC-066FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 30/60頁 |
| 文件大小： | 664K |
| 代理商： | M38198MC-066FP |
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30
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
A-D CONVERTER
The functional blocks of the A-D converter are described below.
A-D Conversion Register (AD) 002D
16
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. This register should not be read dur-
ing A-D conversion.
AD/DA Control Register (ADCON) 002C
16
The AD/DA control register controls the A-D and the D-A conver-
sion process. Bits 0 to 3 of this register select analog input pins.
Bit 4 is the AD conversion completion bit. The value of this bit re-
mains at “0” during an A-D conversion, then changes to “1” when
the A-D conversion is completed.
The A-D conversion starts by writing “0” to this bit. Bit 6 controls
the output of D-A converter.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P7
7
/AN
7
–P7
0
/
AN
0
, P5
7
/S
RDY3
/AN
15
–P5
0
/S
IN2
/AN
8
, and inputs to the compara-
tor.
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
conversion interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(X
IN
) to 500 kHz or more during A-D conversion.
Note :
When using the A-D conversion interrupt, set the INT
4
/AD conver-
sion interrupt switch bit (the bit 5 of the interrupt selection register)
to “1”.
Fig. JA-1 Structure of A-D control register
Analog input pin selection bits
b3 b2 b1 b0
0 0 0 0 : P7
0
/AN
0
0 0 0 1 : P7
1
/AN
1
0 0 1 0 : P7
2
/AN
2
0 0 1 1 : P7
3
/AN
3
0 1 0 0 : P7
4
/AN
4
0 1 0 1 : P7
5
/AN
5
0 1 1 0 : P7
6
/AN
6
0 1 1 1 : P7
7
/AN
7
1 0 0 0 : P5
0
/S
IN2
/AN
8
1 0 0 1 : P5
1
/S
OUT2
/AN
9
1 0 1 0 : P5
2
/S
CLK2
/AN
10
1 0 1 1 : P5
3
/S
RDY2
/AN
11
1 1 0 0 : P5
4
/S
IN3
/AN
12
1 1 0 1 : P5
5
/S
OUT3
/AN
13
1 1 1 0 : P5
6
/S
CLK3
/AN
14
1 1 1 1 : P5
7
/S
RDY3
/AN
15
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (returns “0” when read)
DA output enable bit
0 : Disable
1 : Enable
Not used (returns “0” when read)
b7
AD/DA control register
(ADCON : address 002C
16
)
b0
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