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參數(shù)資料
| 型號： | M38198M9-XXXFS |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 10/60頁 |
| 文件大?。?/td> | 664K |
| 代理商： | M38198M9-XXXFS |
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10
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
I/O PORTS
Direction Registers
The 3819 group has 54 programmable I/O pins arranged in 8 I/O
ports (ports P2
4
–P2
7
, P4
1
–P4
4
, P4
6
, P4
7
, P5–P8, PA, and PB).
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, each pin can be set to be input or
output.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set for output, the value of the
port latch is read, not the value of the pin itself. A pin which is set
for input the value of the pin itself is read because the pin is in
floating state. If a pin set for input is written to, only the port latch
is written to and the pin remains floating.
High-Breakdown-Voltage Output Ports
The 3819 group microprocessors have 7 ports with high-break-
down-voltage pins (ports P0, P1, P2
0
–P2
3
, P3, P8, P9, PA). The
high-breakdown-voltage ports have P-channel open-drain output
with V
CC
–40 V of breakdown voltage.
Each pin in ports P0, P1, P2
0
–P2
3
, P3, and P9 has an internal
pull-down resistor connected to V
EE
. Ports P8 and PA have no in-
ternal pull-down resistors, so that connect an external resistor to
each port. At reset, the P-channel output transistor of each port
latch is turned off, so it becomes V
EE
level (“L”) by the pull-down
resistor.
Writing “1” (weak drivability) to bit 7 of the FLDC mode register 1
(address 0036
16
) shows the rising transition of the output transis-
tors for reducing transient noise. At reset, bit 7 of the FLDC mode
register 1 is set to “0” (strong drivability).
Pin
Name
Input/Output
I/O Format
Non-Port Function
Related SFR
S
Diagram
No.
P0
0
/SEG
32
/
DIG
0
–
P0
7
/SEG
39
/
DIG
7
P1
0
/SEG
40
/
DIG
8
–
P1
7
/DIG
15
P2
0
/DIG
16
–
P2
3
/DIG
19
P2
4
–P2
7
P3
0
/SEG
24
–
P3
7
/SEG
31
P4
0
/INT
0
P4
5
/INT
1
/
ZCR
P4
2
/INT
2
–
P4
4
/INT
4
P4
1
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
TTL level input
CMOS 3-state output
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
CMOS compatible
input level
P4
6
/T1
OUT
,
P4
7
/T3
OUT
CMOS compatible
input level
CMOS 3-state output
Port P0
Port P1
Port P2
Port P3
Port P4
Output
Output
Output
Input/output,
individual bits
Output
Input
Input/output,
individual bits
FLD automatic dis-
play function
FLD automatic dis-
play function
FLD automatic dis-
play function
FLD automatic dis-
play function
External interrupt
input
Zero cross detec-
tion circuit input
(P4
5
)
Timer output
FLDC mode register 1
FLDC mode register 2
Port P0
segment/digit
switch register
FLDC mode register 1
FLDC mode register 2
FLDC mode register 1
FLDC mode register 2
Port P2 digit/port
switch register
FLDC mode register 1
FLDC mode register 2
Interrupt edge
selection register
Zero cross detection
control register
Timer 12 mode register
Timer 34 mode register
(1)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(4)
(8)
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