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參數(shù)資料
| 型號： | M38198EB-XXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 32/60頁 |
| 文件大?。?/td> | 664K |
| 代理商： | M38198EB-XXXFP |
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32
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
G1 (SEG PA)
G2 (SEG PA)
0F80
16
FLD automatic
display RAM
G15 (SEG PA)
G16 (SEG PA)
G1 (SEG P8)
G2 (SEG P8)
0F8F
16
0F90
16
G15 (SEG P8)
G16 (SEG P8)
G1 (SEG P9)
G2 (SEG P9)
0F9F
16
0FA0
16
G15 (SEG P9)
G16 (SEG P9)
G1 (SEG P3)
G2 (SEG P3)
0FAF
16
0FB0
16
G15 (SEG P3)
G16 (SEG P3)
G1 (SEG P0)
G2 (SEG P0)
0FBF
16
0FC0
16
G15 (SEG P0)
G16 (SEG P0)
G1 (SEG P1)
G2 (SEG P1)
0FCF
16
0FD0
16
G15 (SEG P1)
G16 (SEG P1)
0FDF
16
Local
address bus
Main
address bus
Address
decoder
FLD data pointer
(address 0038
16
)
FLD data pointer
reload register
(address 0038
16
)
Timing
generator
FLD blanking interrupt
FLD digit interrupt
PA
1
/SEG
1
PA
2
/SEG
2
PA
3
/SEG
3
PA
4
/SEG
4
PA
5
/SEG
5
PA
6
/SEG
6
PA
7
/SEG
7
0014
16
P8
0
/SEG
8
S/P
S/P
S/P
S/P
S/P
S/P
S/P
PA
0
/SEG
0
S/P
0035
16
8
P8
1
/SEG
9
P8
2
/SEG
10
P8
3
/SEG
11
P8
4
/SEG
12
P8
5
/SEG
13
P8
6
/SEG
14
P8
7
/SEG
15
0010
16
P9
0
/SEG
16
S/P
S/P
S/P
S/P
S/P
S/P
S/P
S/P
0034
16
8
P9
1
/SEG
17
P9
2
/SEG
18
P9
3
/SEG
19
P9
4
/SEG
20
P9
5
/SEG
21
P9
6
/SEG
22
P9
7
/SEG
23
0012
16
P3
0
/SEG
24
8
P0
1
/SEG
33
/DIG
1
P0
2
/SEG
34
/DIG
2
P0
3
/SEG
35
/DIG
3
P0
4
/SEG
36
/DIG
4
P0
5
/SEG
37
/DIG
5
P0
6
/SEG
38
/DIG
6
P0
7
/SEG
39
/DIG
7
S/D
S/D
S/D
S/D
S/D
S/D
S/D
P0
0
/SEG
32
/DIG
0
S/D
0000
16
0032
16
8
P2
1
/DIG
17
P2
2
/DIG
18
P2
3
/DIG
19
0004
16
D/P
D/P
D/P
P2
0
/DIG
16
D/P
4
FLDC mode
register 1
(address 0036
16
)
P1
1
/SEG
41
/DIG
9
P1
2
/DIG
10
P1
3
/DIG
11
P1
4
/DIG
12
P1
5
/DIG
13
P1
6
/DIG
14
P1
7
/DIG
15
0037
16
S/D
P1
0
/SEG
40
/DIG
8
S/D
0002
16
8
P3
1
/SEG
25
P3
2
/SEG
26
P3
3
/SEG
27
P3
4
/SEG
28
P3
5
/SEG
29
P3
6
/SEG
30
P3
7
/SEG
31
0006
16
8
Main
data bus
Local
data bus
0033
16
FLD CONTROLLER
The 3819 group has fluorescent display (FLD) drive and control
circuits.
The FLD controller consists of the following components:
42 pins for segments
20 pins for digits
FLDC mode register 1
FLDC mode register 2
FLD data pointer
FLD data pointer reload register
Port P0 segment/digit switch register
Port P2 digit/port switch register
Port PA segment/port switch register
Port P8 segment/port switch register
96-byte FLD automatic display RAM
The segment pins can be used from 16 up to 42 pins (maximum)
and the digit pins can be used from 6 up to 16 pins (maximum).
The segment and the digit pins can be used up to 52 pins (maxi-
mum) in total.
In the FLD automatic display mode ports P1
2
to P1
7
become digit
pins DIG
10
to DIG
15
automatically.
Fig. KA-1 FLD control circuit block diagram
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