參數(shù)資料
型號(hào)： M38195M1-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 57/60頁(yè)
文件大小： 664K
代理商： M38195M1-XXXFP
57
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
P5
6
/S
CLK3
,
P5
2
/S
CLK2
,
P6
6
/S
CLK11
Serial clock output port
Note :
Ports P8 and PA need external resistors.
C
L
P0, P1, P2
–P2
3
,
P3, P8, P9, PA
High-breakdown-voltage
P-channel open-drain
output port
C
L
(Note)
V
EE
Symbol
t
W(RESET)
t
C(X
IN
)
t
WH(X
IN
)
t
WL(X
IN
)
t
C(Xc
IN
)
t
WH(Xc
IN
)
t
WL(Xc
IN
)
t
C(CNTR)
t
WH(CNTR)
t
WL(CNTR)
t
WH(INT)
t
WL(INT)
t
C(S
CLK
)
t
WH(S
CLK
)
t
WL(S
CLK
)
t
su(S
CLK
–S
IN
)
t
h(S
CLK
–S
IN
)
TIMING REQUIREMENTS
(V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, T
a
= –10 to 85°C, unless otherwise noted)
Parameter
Reset input “L” pulse width
Main clock input cycle time (X
IN
input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (X
CIN
input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
–INT
4
input “H” pulse width
INT
0
–INT
4
input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
Limits
Typ.
Min.
2.0
119
30
30
20
5.0
5.0
4.0
1.6
1.6
80
80
1.0
400
400
200
200
Max.
Unit
μ
s
ns
ns
ns
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
μ
s
ns
ns
ns
ns
SWITCHING CHARACTERISTICS
(V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, T
a
= –10 to 85°C, unless otherwise noted)
Symbol
t
WH(S
CLK
)
t
WL(S
CLK
)
t
d(S
CLK
–S
OUT
)
t
v(S
CLK
–S
OUT
)
t
r(S
CLK
)
t
f(S
CLK
)
t
r(Pch–strg)
t
f(Pch–weak)
Parameter
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output hold time
Serial I/O clock output rising time
Serial I/O clock output falling time
High-breakdown-voltage P-channel open-
drain output rising time (Note 1)
Test conditions
C
L
= 100 pF
C
L
= 100 pF
C
L
= 100 pF
C
L
= 100 pF
C
L
= 100 pF
V
EE
= V
CC
–36 V
Limits
Typ.
Min.
t
c(S
CLK
)
/2–160
t
c(S
CLK
)
/2–160
0
55
1.8
Max.
0.2t
c(S
CLK
)
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
μ
s
Notes 1:
When the bit 7 of the FLDC mode register 1 (address 0036
16
) is at “0”.
2:
When the bit 7 of the FLDC mode register 1 (address 0036
16
) is at “1”.
Fig. ZA-2 Circuit for measuring output switching characteristics
High-breakdown-voltage P-channel open-
drain output falling time (Note 2)
C
L
= 100 pF
V
EE
= V
CC
–36 V
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