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參數(shù)資料
| 型號： | M38073E4-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 35/77頁 |
| 文件大?。?/td> | 1126K |
| 代理商： | M38073E4-XXXFP |
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37
3807 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O
qSerial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during Serial I/O1 opera-
tion.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting the
serial I/O1 mode selection bit (b6) of the serial I/O1 control register
to "1." For clock synchronous serial I/O, the transmitter and the
receiver must use the same clock for serial I/O1 operation. If an
internal clock is used, transmit/receive is started by a write signal to
the Transmit/Receive buffer register (TB/RB) (address:001816).
1/4
XIN
1/4
F/F
P46/SCLK1
Serial I/O1 status register
Serial I/O 1 control register
P47/SRDY1
P44/RXD
P45/TXD
f(XIN)
(f(XCIN) in low-speed mode)
Receive buffer register
Address 001816
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O1 synchronous clock selection bit
Baud rate generator
Division ratio 1/(n+1)
Address 001C16
BRG count source selection bit
Clock control circuit
Falling edge detector
Transmit buffer register
Data bus
Address 001816
Shift clock
Transmit shift register shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001916
Data bus
Address 001A16
Transmit shift register
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transmit/Receive shift clock
(1/2—1/2048 of internal
clock or external clock)
Serial output TxD
Serial input RxD
Write-in signal to transmit/receive
buffer register (address 001816)
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O1
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal SRDY1
Fig. 34. Operation of clock synchronous serial I/O1 function
Fig. 33. Block diagram of clock synchronous serial I/O1
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