參數(shù)資料
型號： M38039MF-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, 1.78 MM PITCH, PLASTIC, SDIP-64
文件頁數(shù)： 32/138頁
文件大?。?/td> 1887K
代理商： M38039MF-XXXSP
Rev.4.01
Nov 14, 2003
page 125 of 136
3803/3804 Group
Table 38 Switching characteristics 1
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Table 39 Switching characteristics 2
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Serial I/O1, serial I/O3 clock output “H” pulse width
Serial I/O1, serial I/O3 clock output “L” pulse width
Serial I/O1, serial I/O3 output delay time (Note 1)
Serial I/O1, serial I/O3 output valid time (Note 1)
Serial I/O1, serial I/O3 clock output rising time
Serial I/O1, serial I/O3 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tWH (SCLK1),
tWH (SCLK3)
tWL (SCLK1),
tWL (SCLK3)
td (SCLK1-TXD1) ,
td (SCLK3-TXD3)
tv (SCLK1-TXD1) ,
tv (SCLK3-TXD3)
tr (SCLK1) , tr (SCLK3)
tf (SCLK1), tf (SCLK3)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Limits
ns
Parameter
Min.
tC(SCLK1)/2–30
tC(SCLK3)/2–30
tC(SCLK1)/2–30
tC(SCLK3)/2–30
–30
tC(SCLK2)/2–160
0
Typ.
10
Max.
140
30
200
30
Symbol
Unit
Notes 1: When the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
When the P35/TXD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”.
2: The XOUT pin is excluded.
Test
conditions
Fig. 105
Serial I/O1, serial I/O3 clock output “H” pulse width
Serial I/O1, serial I/O3 clock output “L” pulse width
Serial I/O1, serial I/O3 output delay time (Note 1)
Serial I/O1, serial I/O3 output valid time (Note 1)
Serial I/O1, serial I/O3 clock output rising time
Serial I/O1, serial I/O3 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tWH (SCLK1),
tWH (SCLK3)
tWL (SCLK1),
tWL (SCLK3)
td (SCLK1-TXD1) ,
td (SCLK3-TXD3)
tv (SCLK1-TXD1) ,
tv (SCLK3-TXD3)
tr (SCLK1) , tr (SCLK3)
tf (SCLK1), tf (SCLK3)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Limits
ns
Parameter
Min.
tC(SCLK1)/2–50
tC(SCLK3)/2–50
tC(SCLK1)/2–50
tC(SCLK3)/2–50
–30
tC(SCLK2)/2–240
0
Typ.
20
Max.
350
50
400
50
Symbol
Unit
Notes 1: When the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
When the P35/TXD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”.
2: The XOUT pin is excluded.
Test
conditions
Fig. 105
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