參數(shù)資料
型號： M38039FFSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-64
文件頁數(shù)： 41/138頁
文件大?。?/td> 1887K
代理商： M38039FFSP
REVISION HISTORY
3803/3804 GROUP DATA SHEET
Rev.
Date
Description
Page
Summary
(3/5)
43
44
45
46
55
63
68
70
71
74
75
78
79
80
84
110
111
114
121
122
123
3.0
06/28/00
Explanations of “qMode selection” of “(5) Pulse width measurement mode” of
“q16-bit Timers” are partly added.
Explanations of “qMode selection” of “(6) Programmable waveform generating
mode” of “q16-bit Timers” are partly added.
Explanations of “qMode selection” of “(7) Programmable one-shot generating
mode” of “q16-bit Timers” are partly added.
Figure 32 is partly revised.
Note into Figure 33 is added.
Explanations of “7. Transmit interrupt request when transmit enable bit is set” are
revised.
Explanations of “7. Transmit interrupt request when transmit enable bit is set” are
revised.
Explanations of “D-A CONVERTER” are partly eliminated.
Figure 64 is partly revised.
Explanations of “[I2C Slave Address Registers 0 to 2 (S0D0 to S0D2)]” are partly
added.
Explanations of “Bit 3: Arbitration lost detecting flag (AL)” of “[I2C Status Register
(S1)]” are partly added.
Explanations of “Bit 7: Communication mode specification bit (master/slave
specification bit: MST)” of “[I2C Status Register (S1)]” are partly revised.
“Bit 7: Data receive mode at Stop/Low-speed mode bit (STR)” of “[I2C
START/STOP Condition Control Register (S2D)]” is eliminated.
Explanations of b7 into Figure 74 are revised.
“Bit 4: Time out flag (TIOUT)” of “[I2C Special Mode Status Register (S3)]” is
eliminated.
Figure 75 is partly revised.
“Bit 0: I2C time out control bit (TOEN)” is eliminated.
“Bit 4: Time out flag clear bit (TOFCL)” is eliminated.
Figure 76 is partly revised.
Note into Figure 76 is added.
Explanations of “RESET CIRCUIT” are partly revised.
Explanations of “Functional Outline (CPU reprogramming mode)” of “(3) Flash
memory mode 3 (CPU reprogramming mode)” are partly eliminated.
Explanations of b3, b1, b0 into Figure 103 are partly revised.
Explanations of “Instruction Execution Time” are partly reviesd.
Table 31 is partly eliminated.
Limits of RO into Table 34 are revised.
Limits and unit of tw(RESET) into Table 35 are revised.
Symbol of th(SCLK3–RxD3) into Table 35 is revised.
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