參數(shù)資料
型號(hào)： M38037M8H-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 69/119頁
文件大小： 1818K
代理商： M38037M8H-XXXHP
Rev.3.11
Apr 5, 2006
Page 51 of 113
REJ03B0017-0311
3803 Group (Spec.H)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O3 mode selection bit (b6) of the serial I/O3
control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in a memory. Since the
shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer register, and receive data is
read from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig 43. Block diagram of UART serial I/O3
Fig 44. Operation of UART serial I/O3
f(XIN)
1/4
OE
PE FE
1/16
Data bus
Receive buffer register 3
Address 003016
Receive shift register 3
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator 3
Frequency division ratio 1/(n+1)
Address 002F16
ST/SP/PA generator
Transmit buffer register 3
Transmit shift register 3
Address 003016
Transmit shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address 003116
ST detector
SP detector
UART3 control register
Address 003316
Character length selection bit
Address 003216
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O3 synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O3 status register
Serial I/O3 control register
P36/SCLK3
P34/RXD3
P35/TXD3
(f(XCIN) in low-speed mode)
TSC=0
TBE=1
RBF=0
TBE=0
RBF=1
TBE=1
TSC=1*
ST
D0
D1
SP
D0
D1
ST
SP
Transmit or
receive clock
Transmit buffer
write signal
Serial output
TXD3
Receive buffer
read signal
Serial input
RXD3
* Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O3 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0.
ST
D0
D1
SP
D0
D1
ST
SP
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