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| 型號(hào)： | M38031FFL-XXXKP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 0 MHz to 200 MHz; Outputs: 3 |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 28/119頁 |
| 文件大?。?/td> | 1575K |
| 代理商： | M38031FFL-XXXKP |
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Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 28 of 117
3803 Group (Spec.L)
Interrupt Request Generation, Acceptance, and Handling
Interrupts have the following three phases.
(i)
Interrupt Request Generation
An interrupt request is generated by an interrupt source
(external interrupt signal input, timer underflow, etc.) and
the corresponding request bit is set to “1”.
(ii) Interrupt Request Acceptance
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance
conditions (interrupt request bit, interrupt enable bit, and
interrupt disable flag) and interrupt priority levels for
accepting interrupt requests. When two or more interrupt
requests are generated simultaneously, the highest priority
interrupt is accepted. The value of interrupt request bit for
an unaccepted interrupt remains the same and acceptance is
determined at the next interrupt acceptance timing point.
(iii) Handling of Accepted Interrupt Request
The accepted interrupt request is processed.
Figure 22 shows the time up to execution in the interrupt
processing routine, and Figure 23 shows the interrupt sequence.
Figure 24 shows the timing of interrupt request generation,
interrupt request bit, and interrupt request acceptance.
Interrupt Handling Execution
When interrupt handling is executed, the following operations
are performed automatically.
(1) Once the currently executing instruction is completed, an
interrupt request is accepted.
(2) The contents of the program counters and the processor
status register at this point are pushed onto the stack area in
order from 1 to 3.
1.High-order bits of program counter (PCH)
2.Low-order bits of program counter (PCL)
3.Processor status register (PS)
(3) Concurrently with the push operation, the jump address of
the corresponding interrupt (the start address of the interrupt
processing routine) is transferred from the interrupt vector to
the program counter.
(4) The interrupt request bit for the corresponding interrupt is
set to “0”. Also, the interrupt disable flag is set to “1” and
multiple interrupts are disabled.
(5) The interrupt routine is executed.
(6) When the RTI instruction is executed, the contents of the
registers pushed onto the stack area are popped off in the
order from 3 to 1. Then, the routine that was before running
interrupt processing resumes.
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each
interrupt to execute the interrupt processing routine.
<Notes>
The interrupt request bit may be set to “1” in the following cases.
When setting the external interrupt active edge
Related registers:Interrupt edge selection register
(address 003A
16)
Timer XY mode register (address 0023
16
)
Timer Z mode register (address 002A
16
)
When switching the interrupt sources of an interrupt vector
address where two or more interrupt sources are assigned
Related registers:Interrupt source selection register
(address 0039
16
)
If it is not necessary to generate an interrupt synchronized with
these settings, take the following sequence.
(1) Set the corresponding enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit (the active edge switch
bit) or the interrupt source bit.
(3) Set the corresponding interrupt request bit to “0” after one
or more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
Fig 22. Time up to execution in interrupt routine
Fig 23. Interrupt sequence
7 cycles
Interrupt request
generated
Interrupt request
acceptance
Interrupt routine
starts
Interrupt sequence
0 to 1*
7 to 23 cycles
* When executing DIV instruction
Main routine
Stack push and
Vector fetch
Interrupt handling
routine
φ
SYNC
RD
WR
Push onto stack
Vector fetch
Address bus
Data bus
Execute interrupt
routine
PC
S,SPS
S-1,SPS S-2,SPS
B
L
B
H
A
L
,A
H
Not used
PC
H
PC
L
PS
A
L
A
H
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH: Vector address of each interrupt
AL, AH: Jump destination address of each interrupt
SPS
: “00
16
” or “01
16
”
([SPS]
is a page selected by the stack page selection bit of CPU mode register.)
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