參數(shù)資料
型號(hào)： M38025E6
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 30/51頁(yè)
文件大?。?/td> 692K
代理商： M38025E6
MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
30
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator be-
tween X
IN
and X
OUT
. To supply a clock signal externally, input it to
the X
IN
pin and make the X
OUT
pin open.
Oscillation control
Stop Mode
If the STP instruction is executed, the internal clock
φ
stops at an
“H”. Timer 1 is set to “01
16
” and prescaler 12 is set to “FF
16
”.
Oscillator restarts when an external interrupt is received, but the
internal clock
φ
remains at an “H” until timer 1 underflow.
This allows time for the clock circuit oscillation to stabilize.
If oscillator is restarted by a reset, no wait time is generated, so
keep the RESET pin at an “L” level until oscillation has stabilized.
Wait Mode
If the WIT instruction is executed, the internal clock
φ
stops at an
“H” level, but the oscillator itself does not stop. The internal clock
restarts if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
To ensure that interrupts will be received to release the STP or
WIT state, interrupt enable bits must be set to “1” before the STP
or WIT instruction is executed.
When the STP status is released, prescaler 12 and timer 1 will
start counting and reset will not be released until timer 1
underflows, so set the timer 1 interrupt enable bit to “0” before the
STP instruction is executed.
Fig. 31 Block diagram of clock generating circuit
Fig. 30 External clock input circuit
Fig. 29 Ceramic resonator circuit
C
OUT
X
IN
X
OUT
C
IN
X
IN
X
OUT
Open
External oscillation
circuit
Vss
Vcc
1/8
X
OUT
X
IN
R
S
Q
STP instruction
WIT
instruction
R
S
Q
R
S
Q
Reset
STP instruction
Timer 1
ONW
control
Prescaler 12
1/2
φ
output
Internal clock
φ
Rd
Rf
ONW pin
Single-chip mode
Reset
Interrupt request
Interrupt disable
flag (I)
FF
16
01
16
Reset or STP instruction
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