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參數(shù)資料
| 型號(hào)： | AM79C970AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 205/219頁(yè) |
| 文件大小： | 1065K |
| 代理商： | AM79C970AKCW |
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D-1
Am79C970A
Look-Ahead Packet Processing (LAPP) Concept
APPENDIX D
INTRODUCTION OF THE LAPP CONCEPT
A driver for the PCnet-PCI II controller would normally
require that the CPU copy receive frame data from the
controllers buffer space to the applications buffer space
after the entire frame has been received by the control-
ler. For applications that use a ping-pong windowing
style, the traffic on the network will be halted until the
current frame has been completely processed by the
entire application stack. This means that the time be-
tween last byte of a receive frame arriving at the clients
Ethernet controller and the clients transmission of the
first byte of the next outgoing frame will be separated by:
1. The time that it takes the clients CPUs interrupt
procedure to pass software control from the cur-
rent task to the driver
2. plus the time that it takes the client driver to pass
the header data to the application and request an
application buffer
3. plus the time that it takes the application to gener-
ate the buffer pointer and then return the buffer
pointer to the driver
4. plus the time that it takes the client driver to trans-
fer all of the frame data from the controllers buffer
space into the applications buffer space and then
call the application again to process the complete
frame
5. plus the time that it takes the application to proc-
ess the frame and generate the next outgoing
frame
6. plus the time that it takes the client driver to set up
the descriptor for the controller and then write a
TDMD bit to CSR0
The sum of these times can often be about the same as
the time taken to actually transmit the frames on the
wire, thereby yielding a network utilization rate of less
than 50%.
An important thing to note is that the PCnet-PCI II con-
trollers data transfers to its buffer space are such that
the system bus is needed by the PCnet-PCI II controller
for approximately 4% of the time. This leaves 96% of the
system bus bandwidth for the CPU to perform some of
the inter-frame operations in advance of the completion
of network receive activity, if possible. The question
then becomes: how much of the tasks that need to be
performed between reception of a frame and transmis-
sion of the next frame can be performed before the re-
ception of the frame actually ends at the network, and
how can the CPU be instructed to perform these tasks
during the network reception time
The answer depends upon exactly what is happening in
the driver and application code, but the steps that can be
performed at the same time as the receive data are ar-
riving include as much as the first 3 steps and part of the
4
th
step shown in the sequence above. By performing
these steps before the entire frame has arrived, the
frame throughput can be substantially increased.
A good increase in performance can be expected when
the first 3 steps are performed before the end of the net-
work receive operation. A much more significant per-
formance increase could be realized if the PCnet-PCI II
controller could place the frame data directly into the ap-
plications buffer space; (i.e., eliminate the need for step
4.) In order to make this work, it is necessary that the ap-
plication buffer pointer be determined before the frame
has completely arrived, then the buffer pointer in the
next descriptor for the receive frame would need to be
modified in order to direct the PCnet-PCI II controller to
write directly to the application buffer. More details on
this operation will be given later.
An alternative modification to the existing system can
gain a smaller, but still significant improvement in per-
formance. This alternative leaves step 4 unchanged in
that the CPU is still required to perform the copy opera-
tion, but it allows a large portion of the copy operation to
be done before the frame has been completely received
by the controller; i.e., the CPU can perform the copy op-
eration of the receive data from the PCnet-PCI II control-
lers buffer space into the application buffer space before
the frame data has completely arrived from the network.
This allows the copy operation of step 4 to be performed
concurrently with the arrival of network data, rather
than sequentially, following the end of network
receive activity.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AVC\\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVC\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:AMD 功能描述: |
| AM79C970AVC-G | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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