參數(shù)資料
型號： M38020M1
廠商： Mitsubishi Electric Corporation
英文描述： Single Output LDO, 800mA, Fixed(2.5V), Internal Current limit, Thermal Overload Protection 8-SON 0 to 125
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 14/51頁
文件大?。?/td> 692K
代理商： M38020M1
MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
21
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns "1" when read)
Serial I/O1 status register
(SIO1STS : address 0019 16)
Serial I/O1 control register
(SIO1CON : address 001A 16)
b0
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
SRDY1 output enable bit (SRDY)
0: P47 pin operates as ordinaly I/O pin
1: P47 pin operates as S RDY1 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P44 to P47 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P44 to P47 operate as serial I/O pins)
b7
UART control register
(UARTCON : address 001B 16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return "1" when read)
b0
Fig. 14 Structure of serial I/O control registers
相關(guān)PDF資料
PDF描述
M38020M2 Single Output LDO, 800mA, Fixed(2.5V), Internal Current limit, Thermal Overload Protection 4-SOT-223 -40 to 125
M38020M3 Single Output LDO, 800mA, Fixed(3.3), Internal Current limit, Thermal Overload Protection 4-SOT-223 0 to 125
M38020M4 Single Output LDO, 800mA, Fixed(3.3), Internal Current limit, Thermal Overload Protection 8-SON 0 to 125
M38020M1D192FP Single Output LDO, 800mA, Fixed(2.5V), Internal Current limit, Thermal Overload Protection 3-PFM 0 to 125
M38020M1D192FS Single Output LDO, 800mA, Fixed(2.5V), Internal Current limit, Thermal Overload Protection 4-SOT-223 -40 to 125
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