參數(shù)資料
型號： M38006M2-XXXHP
廠商： Mitsubishi Electric Corporation
元件分類： 串行ADC
英文描述： 8-Bit 37.9 kSPS ADC Serial Out, Ratiometric Op or Vcc Ref, TTL/MOS Input & Output Compatible, 8 Ch. 20-TSSOP 0 to 70
中文描述： 8位單片機(jī)
文件頁數(shù)： 42/173頁
文件大?。?/td> 4203K
代理商： M38006M2-XXXHP
1-28
HARDWARE
3800 GROUP USER’S MANUAL
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator be-
tween X
IN
and X
OUT
. To supply a clock signal externally, input it to
the X
IN
pin and make the X
OUT
pin open.
Oscillation control
Stop Mode
If the STP instruction is executed, the internal clock
φ
stops at “H”.
Timer 1 is set to “01
16
” and prescaler 12 is set to “FF
16
”.
Oscillator restarts when an external interrupt is received, but the
internal clock
φ
remains at “H” until timer 1 underflows.
This allows time for the clock circuit oscillation to stabilize.
If oscillator is restarted by a reset, no wait time is generated, so
keep the RESET pin at “L” level until oscillation has stabilized.
Wait Mode
If the WIT instruction is executed, the internal clock
φ
stops at an
“H” level, but the oscillator itself does not stop. The internal clock
restarts if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
To ensure that interrupts will be received to release the STP or
WIT state, interrupt enable bits must be set to “1” before the STP
or WIT instruction is executed.
When the STP status is released, prescaler 12 and timer 1 will
start counting and reset will not be released until timer 1
underflows, so set the timer 1 interrupt enable bit to “0” before the
STP instruction is executed.
Fig. 27 Block diagram of clock generating circuit
Fig. 26 External clock input circuit
Fig. 25 Ceramic resonator circuit
FUNCTIONAL DESCRIPTION
C
OUT
X
IN
X
OUT
C
IN
X
IN
X
OUT
Open
External oscillation
circuit
Vss
Vcc
1/8
X
OUT
X
IN
R
S
Q
STP instruction
WIT
instruction
R
S
Q
R
S
Q
Reset
STP instruction
Timer 1
ONW
control
Prescaler 12
1/2
φ
output
Internal clock
φ
Rd
Rf
ONW pin
Single-chip mode
Reset
Interrupt request
Interrupt disable
flag (I)
FF
16
01
16
Reset or STP instruction
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