APPLICATION
2.6 Processor mode
2-67
3802 GROUP USER’S MANUAL
Fig. 2.6.6 Write-cycle (W control, SRAM)
td(AH
–
WR)
t
WL
(WR)
td(WR
–
DB)
tsu(D)
W
(WR of 3802)
65 ns (max)
35 ns (min)
Address (low-order)
Address (high-order)
Data
DQ
1
–DQ
8
(Port P2)
S
(A15)
OE
(RD of 3802)
“ H ” level
125 ns - 10 ns (min)
125 ns - 35 ns (min)
td(AH
–
WR)
t
WL
(WR)
td(WR
–
DB)
tsu(D)
:
WR delay time after outputting address of 3802
:
WR pulse width of 3802
:
Data bus delay time after WR of 3802
:
Data setup time of M5M5256BP
A
0
–A
7
(Port P0)
A
8
–A
14
(Port P1)