參數(shù)資料
型號: M38002E2FP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, PLASTIC, QFP-64
文件頁數(shù): 101/173頁
文件大?。?/td> 4203K
代理商: M38002E2FP
HARDWARE
1-19
3800 GROUP USER’S MANUAL
Fig. 13 Interrupt control
Fig. 14 Structure of interrupt-related registers
FUNCTIONAL DESCRIPTION
b7
b0
b7
b0
b7
b0
b7
b0
b7
b0
Interrupt edge selection register
INT0 active edge selection bit
INT1 active edge selection bit
INT2 active edge selection bit
INT3 active edge selection bit
INT4 active edge selection bit
INT5 active edge selection bit
Not used (return “0” when read)
(INTEDGE : address 003A16)
Interrupt request register 1
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Interrupt control register 1
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
(IREQ1 : address 003C16)
(ICON1 : address 003E16)
Interrupt request register 2
CNTR0 interrupt request bit
CNTR1 interrupt request bit
INT2 interrupt request bit
INT3 interrupt request bit
INT4 interrupt request bit
INT5 interrupt request bit
Not used (return “0” when read)
(IREQ2 : address 003D16)
Interrupt control register 2
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
INT2 interrupt enable bit
INT3 interrupt enable bit
INT4 interrupt enable bit
INT5 interrupt enable bit
Not used (return “0” when read)
(Do not write “1” to this bit)
0 : No interrupt request issued
1 : Interrupt request issued
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F16)
0 : Falling edge active
1 : Rising edge active
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
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