APPLICATION
2.2 Timer
2-10
3800 GROUP USER’S MANUAL
Fig. 2.2.8 Structure of Interrupt control register 1
Fig. 2.2.9 Structure of Interrupt control register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0
B
0
Function
At reset
R W
0
1
2
3
0
0
0
Interrupt control reigster 2 (ICON2) [Address : 3F
16
]
Name
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
INT
2
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
INT
3
interrupt enable bit
5
6
7
0
0 : Interrupt disabled
1 : Interrupt enabled
Fix these bits to “0.”
INT
5
interrupt enable bit
4
0
INT
4
interrupt enable bit
0
0
AAAAAAAAAAAAA
Timer 1 interrupt enable bit
Timer Y interrupt enable bit
AAAAAAAAAAAAA
5
AAAAAAAAAAAAAAAA
4
Timer X interrupt enable bit
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
0
0
0
Interrupt control register 1 (ICON1) [Address : 3E
16
]
Name
INT
0
interrupt enable bit
INT
1
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
AAAA
7
0
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O transmit interrupt
enable bit
Serial I/O receive interrupt
enable bit