參數資料
型號： M37920S4CGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 20 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數： 7/40頁
文件大小： 675K
代理商： M37920S4CGP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
14
INPUT/OUTPUT PINS
Each of ports P3 to P9 and P12 has an direction register, and each
bit can be programmed for input or output. A pin becomes an output
pin when the corresponding bit of direction register is “1”, and an in-
put pin when it is “0”.
When a pin is programmed as an output pin, the data written to its
port latch is output to the output pin. When a pin is programmed as
an output pin, the contents of the port latch are read out instead of
the value of the pin. Accordingly, a previously output value can be
read out correctly even when the output “H” voltage is lowered or the
output “L” voltage is raised, owing to an external load, etc.
A pin programmed as an input pin is placed in the flooting state, and
the value input to the pin can be read out correctly. When a pin is pro-
grammed as an input pin, the data can be written only in the port
latch, and the pin remains floating.
Each of Figures 8 and 9 shows the block diagram for each port pin.
Table 2. Correspondence between external buses, bus control sig-
nals, and programmable I/O port pins
External buses,
Bus control signals
A0 to A7,
A8 to A15,
A16 to A23
0
Standby state select bit
A0 to A7,
A8 to A15,
A16 to A23
1
D0 to D7,
D8 to D15 (Note 1)
D0 to D7,
D8 to D15
P100 to P107 (Note 2),
P110 to P117 (Note 2),
P00 to P07 (Note 2)
P10 to P17 (Note 2),
P20 to P27
RD, BLW,
BHW
RD, BLW,
BHW (Note 1)
P31, P32 (Note 2),
P33
CS0
P90 (Note 2)
Notes 1: When the external data bus width = 8 bits (BYTE = VCC level),
this becomes a programmable I/O port pin, regardless of the
standby state select bit’s contents.
2: Pin functions of port pins P0, P1, P31, P32, P90, P10, P11 are
not shown in the pin configuration. However, relationship with
corresponding bus signals and ports is listed in Table 2. For
the addresses of these port’s registers and direction registers,
refer to the location of the perpheral devices’ control registers
(Figures 2 and 3).
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