Page 81,
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Line 12
(6/7)
Corrections and Supplementary Explanation for M37906MxX Datasheet (Rev.C) No.6
after the oscillation circuit has been restarted
Page 79,
Fig. 87
Page 79,
Left column
Line 10
after the oscillation circuit and PLL circuit have been
restarted
Particular function register 1
STP-instruction-execution status bit (Note 1)
0: Normal operation.
1: STP instruction has been executed.
10
2
43
5
00
WIT-instruction-execution status bit (Note 1)
0: Normal operation.
1: WIT instruction has been executed.
System clock stop select bit at WIT (Note 2)
0: In wait mode, system clocl fsys is active.
1: In wait mode, system clock fsys is stopped.
Notes 1: Even when “1” is written, the bit status will
not change.
Notes 1: Even when “1” is try to be written, the bit
status will not change.
Page 80,
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Line 5
, and divide clocks Wf32 and Wf512 are inactive with the
“L” state.
, and divide clocks Wf32 and Wf512 are stopped in the
“L” state.
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Lines 6, 7
, and peripheral devices’ clock f1 to f4096 remain
operating. Therefore, BIU and CPU are stopped,
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Lines 9, 10
, which use the peripheral devices’ clocks f 1 to f4096,
are still operating. Note that the watchdog timer is stopped.
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Left column
Lines 13, 14
, and input clock fXIN are operating, while system clock
fsys,
φBIU, φCPU, and peripheral devices’ clocks stop
operating.
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Lines 16, 17
, Wf32 and Wf512, are stopped. At this time, timers A
and B operate only in the event counter mode,
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Line 21
the system clocks stop select bit at WIT is to be set to
“1”
, and peripheral devices’ clocks f1 to f4096 remain
active. Therefore, BIU and CPU are inactive,
Page 80,
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Line 26
, and clock input fXIN are operating in the WIT mode,
Page 81,
Left column
Line 4
(1) Stop of system clock in wait mode
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Line 6
, if the internal peripheral devices need not to operate,
the system clock stop select bit
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Line 8
and peripheral devices’ clock stop their operations,
and
Page 81,
Left column
Line 11
(2) Stop of oscillation circuit
When an externally-generated-stable clock is input to pin
XIN,
Page 78,
Table 11
Stopped
Inactive
Notes 1: , the oscillation circuit stops. Also, clock input
from pin XIN available.
2: , the PLL circuit stops.
Notes 1: , the oscillation circuit is inactive. Also, clock
input from pin XIN is allowed.
2: , the PLL circuit is inactive.
Page 79,
Left column
Line 3
(bit 5 of the clock control register) = “1”,
(bit 5 of the clock control register 0) = “1”,
Page
Error
Correction
Particular function register 1
STP-instruction-execution status bit (Note 1)
0: Normal operation.
1: STP instruction is under execution.
10
2
43
5
00
WIT-instruction-execution status bit (Note 1)
0: Normal operation.
1: WIT instruction is under execution.
System clock stop select bit at WIT (Note 2)
0: In wait mode, system clocl fsys is active.
1: In wait mode, system clock fsys is inactive.
When an externally-generated stable clock is input to pin
XIN,
(2) Inactive oscillation circuit
and peripheral devices’ clock are inactive, and
, if the internal peripheral devices need not to operate,
when the system clock stop select bit
(1) Inactive system clock in wait mode
, and clock input fXIN are active in the WIT mode,
the system clocks stop select bit at WIT needs to be
set to “1”
, Wf32 and Wf512, become inactive. At this time, timers
A and B are active only in the event counter mode,
, and input clock fXIN are active, while system clock
fsys,
φBIU, φCPU, and peripheral devices’ clocks are inactive.
, which use the peripheral devices’ clocks f 1 to f4096,
are still active. Note that the watchdog timer is inactive.