參數(shù)資料
型號(hào)： M37905M6C-XXXSP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, 1.78 MM PITCH, PLASTIC, SDIP-64
文件頁(yè)數(shù)： 93/105頁(yè)
文件大?。?/td> 1040K
代理商： M37905M6C-XXXSP
85
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
param
etric
lim
its are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 96 Bit configuration of particular function select register 1
Fig. 97 Bit configuration of watchdog timer frequency select register
76543210
Watchdog timer frequency select register
Watchdog timer frequency select bit
0 : Select W f512
1 : Select W f32
Watchdog timer clock source select bits at STP termination
0 0 : fX32
0 1 : fX16
1 0 : fX128
1 1 : fX64
76543210
Address
6116
When the external clock input select bit (bit 1 of the particular func-
tion select register 0) = “0” or the system clock select bit (bit 5 of the
clock control register 0) = “1”, the watchdog timer will start counting
down with one of the above divide clocks, fX16 to fX128, after the os-
cillation circuit and PLL circuit have been restarted their operations
owing to an interrupt. The most significant bit of the watchdog timer
reaching “0”, supply of
φBIU and φCPU restarts.
On the other hand, when the external clock input select bit = “1 ” and
the system clock select bit = “0”, supply of
φBIU and φCPU will restart
immediately after the oscillation circuit and PLL circuit have been re-
started their operations owing to an interrupt. (In actual fact, after the
selected one of the above divide clocks, fX16 to fX128, has been
changed from “H” to “L”, this supply will restart.)
7
6
543
2
1
0
Particular function select register 1
STP-instruction-execution status bit (Note 1)
0: Normal operation.
1: STP instruction is under execution.
WIT-instruction-execution status bit (Note 1)
0: Normal operation.
1: WIT instruction is under execution.
Fix this bit to “0”.
System clock stop select bit at WIT (Note 2)
0: In wait mode, system clock fsys is active.
1: In wait mode, system clock fsys is inactive.
Fix this bit to “0”.
Timer B2 clock source select bit
Valid in event counter mode:
0: Clock input from pin TB2IN is counted.
1: fX32 (f(XIN)/32) is counted.
Address
6316
Notes 1: At power-on reset, this bit becomes “0”. At hardware reset or software reset, this bit
retains the value just before reset. Even when “1” is try to be written, the bit status will
not change.
2: Setting this bit to “1” must be performed just before execution of the WIT instruction.
Also, after the wait state is terminated, this bit must be cleared to “0” immediately.
42
00
相關(guān)PDF資料
PDF描述
M37905M8C-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP64
M37905M8C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP64
M37905M6C-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP64
M37906M4H-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
M37906M6C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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