
88
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
RDY input (when 3-
φ access in high-speed running)
HOLD input
Test conditions
VCC = 5 V±10 %
RDY input, HOLD input : VIL = 1.0 V, VIH = 4.0 V
HLDA output
: VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
φ1
RD,WR
RDY input
tsu(RDY-
φ1)
th(
φ1-RDY)
V RDY input is always sampled at the falling edge of
φ1 just before the RD and WR signals’ rise regardless of the bus mode and the number of waits.
φ1
HOLD input
HLDA output
RD
WR
BHE output
A0–A7 output
A8–A15 output
A16–A23 output
D0–D7 output
D8–D15 output
(BYTE =“L”)
tsu(HOLD-
φ1)
td(
φ1-HLDA)
tpxz(HLDA-RDZ)
tpxz(HLDA-WRZ)
tpxz(HLDA-BHE)
tpxz(HLDA-AZ)
tpxz(HLDA-DLZ/DHZ)
tpzx(HLDA-RDZ)
tpzx(HLDA-WRZ)
tpzx(HLDA-BHE)
tpzx(HLDA-AZ)
tpzx(HLDA-DLZ/DHZ)
td(
φ1-HLDA)
th(
φ1-HOLD)
Hi-Z