參數(shù)資料
型號: M37754M8C-XXXGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 53/114頁
文件大?。?/td> 1116K
代理商: M37754M8C-XXXGP
43
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pulse mode 0
This mode divides a pulse output port into 4 bits and 4 bits and indi-
vidually controls them.
When setting the pulse output mode select bit to “0”, and setting bits
2 and 1 to “0” and bit 0 to “1” of the waveform output select bits, four
of RTP13, RTP12, RTP11, and RTP10 become the pulse output
ports with RTP1 selected.
When setting the pulse output mode select bit to “0”, and setting bits
2 and 0 to “0” and bit 1 to “1” of the waveform output select bits, four
of RTP03, RTP02, RTP01, RTP00 become the pulse output ports
with RTP0 selected.
When setting the pulse output mode select bit to “0”, and setting bit
2 to “0” and bits 1 and 0 to “1” of the waveform output select bits,
the following two groups become the pulse output ports with RTP1
and RTP0 selected:
Four of RTP13, RTP12, RTP11, RTP10
Four of RTP03, RTP02, RTP01, RTP00.
Each time the contents of timer A1 counter become 000016, the
contents of pulse output data register 1 (low-order 4 bits at address
1C16) corresponding to RTP13, RTP12, RTP11, RTP10 are output
from ports.
Each time the contents of timer A0 counter become 000016, the
contents of pulse output data register 0 (low-order 4 bits at address
1D16) corresponding to RTP03, RTP02, RTP01, RTP00 are output
from ports.
When writing “0” to the specified bit of pulse output data register, “L”
level is output from the pulse output port when the contents of cor-
responding timer counter become 000016; when writing “1” to it, “H”
level is output from the pulse output port.
Note : Only when bit 5 of the particular function select register 1
(in Fig. 15) is set to “1”, this register’s contents can be
changed from the status after reset (in Fig.76).
Waveform output mode register 1A16
Waveform output select bits
000 : Parallel port
001 : RTP1 selected
(Valid in pulse mode 0)
010 : RTP0 selected
(Valid in pulse mode 0)
011 : In pulse mode 0
RTP1 and RTP0 selected
In pulse mode 1
RTP1, RTP03, RTP02,
RTP01, RTP00 selected
Polarity select bit
(Valid for RTP0 in pulse mode 0)
0 : Positive polarity
1 : Negative polarity
Pulse width modulation select bit 0
(Valid for RTP1 in pulse mode 0;
Valid for RTP1, RTP03, RTP02 in
pulse mode 1)
0 : No modulation by timer A2
1 : Modulation by timer A2
Pulse width modulation select bit 1*
(Valid in pulse mode 1)
0 : Modulation by timer A2
1 : Modulation for RTP03, RTP02
by timer A2
Modulation for RTP11, RTP10
by timer A3
Modulation for RTP13, RTP12
by timer A4
* when selecting pulse mode 0, fix
this bit to “0”.
Waveform output control bit 0
0 : In pulse mode 0
Disable RTP0 waveform output
In pulse mode 1
Disable RTP01, RTP00 waveform
output
1 : In pulse mode 0
Enable RTP0 waveform output
In pulse mode 1
Enable RTP01, RTP00 waveform
output
Waveform output control bit 1
0 : In pulse mode 0
Disable RTP1 waveform output
In pulse mode 1
Disable RTP1, RTP03, RTP02
waveform output
1 : In pulse mode 0
Enable RTP1 waveform output
In pulse mode 1
Enable RTP1, RTP03, RTP02
waveform output
76543210
Address
Timer A0 mode register
5616
Timer A1 mode register
5716
100 : Fix to “100” in pulse output port mode
× : Not used in pulse output port mode
00 : Fix to “00” in pulse output port mode
Clock source select bit
00 : Pf2 selected
01 : Pf16 selected
10 : Pf64 selected
11 : Pf512 selected
76543210
0
1
×
0
Address
Fig. 49 Bit configuration of waveform output mode register in pulse
output port mode
Fig. 50 Bit configuration of timer A1 and A0 mode registers in pulse
output port mode
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