參數(shù)資料
型號: M37753M8C-XXXHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, QFP-80
文件頁數(shù): 80/110頁
文件大?。?/td> 1439K
代理商: M37753M8C-XXXHP
MITSUBISHI MICROCOMPUTERS
M37753M8C-XXXFP, M37753M8C-XXXHP
M37753S4CFP, M37753S4CHP
70
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
Bits 0 and 1 of processor mode register 0 (address 5E16) shown in
Figure 84 are used to select any mode of the single-chip mode, the
memory expansion mode and the microprocessor mode.
Ports P0 to P3 and a part of port P4 are used as I/O pins of address,
data, and control signals in the modes except the single-chip mode.
Figure 85 shows the functions of ports P0 to P4 in each mode.
The external memory area depends on the mode. Figure 86 shows
the memory map for each mode. Refer to Figure 1 for the addresses
of RAM and ROM in the single-chip mode. The external memory
area can be accessed in the modes except the single-chip mode.
The access to the external memory is affected by the BYTE pin.
BYTE pin
When accessing the external memory, the level of the BYTE pin is
used to determine whether to use the data bus as 8-bit width or 16-
bit width.
The data bus has a width of 16 bits when the level of the BYTE pin is
“L”, and ports P1 and P2 become the data I/O pins.
The data bus has a width of 8 bits when level of the BYTE pin is “H”,
and port P2 becomes data I/O pins.
When accessing the internal memory, the data bus always has a
width of 16 bits regardless of the BYTE pin level.
0
76543210
Processor mode register 0
5E16
Processor mode bits
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Do not select.
Internal memory access bus cycle select bit (Note)
; Internal memory access condition in high-speed running
0 : 2-
φ access for internal RAM; 3-φ access for internal ROM and SFR
1 : 2-
φ access for internal RAM, internal ROM and SFR
Software reset bit
Reset occurs when writing “1” to this bit
Interrupt priority detection time select bit
0 0 : Select case 0 shown in Figure 13
0 1 : Select case 1 shown in Figure 13
1 0 : Select case 2 shown in Figure 13
Test mode bit
This bit must be fixed to “0.”
Clock
φ1 output select bit
0 : No
φ1 output
1 :
φ1 output
Address
Note : Clear bit 2 to “0” in low-speed running.
Fig. 84 Processor mode register 0 bit configuration
相關(guān)PDF資料
PDF描述
M37753S4CHP 16-BIT, 40 MHz, MICROCONTROLLER, PQFP80
M37753M8C-XXXFP 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP80
M37753S4CFP 16-BIT, 40 MHz, MICROCONTROLLER, PQFP80
M37753S4CFP 16-BIT, 40 MHz, MICROCONTROLLER, PQFP80
M37753M8C-XXXHP 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP80
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