
10: 2D BITBLT ENGINE
2-58
EPSON
S1D13806 SERIES PROGRAMMING NOTES
AND EXAMPLES (X28B-G-003-01)
10.2.1 Write BitBLT with ROP
The Write BitBLT increases the speed of transferring data from system memory to the display
buffer.
The Write BitBLT with ROP fills a specified area of the display buffer with data supplied by the
CPU. This BitBLT is typically used to copy a bitmap image from system memory to the display
buffer. The Write BitBLT supports all 16 ROPs, although the most frequent ROP is ROP 0Ch (Copy
Source into Destination). It also supports both Destination Linear and Destination Rectangular
modes.
The Write BitBLT requires the CPU to provide data. The BitBLT engine expects to receive a certain
number of WORDS. For 16 bpp color depths, the number of WORDS is the same as the number of
pixels due to the fact that each pixel is one WORD wide. The number of WORD writes the BitBLT
engine expects is calculated using the following formula.
nWORDS = nPixels
= BitBLTWidth
× BitBLTHeight
For 8 bpp color depths, the formula must take into consideration that the BitBLT engine accepts
only WORD accesses and each pixel is one BYTE. The BitBLT engine needs to know whether the
first pixel of a line is stored in the low byte or high byte. This is determined by bit 0 of the Source
Start Address Register 0 (REG[104h]). If the Source Phase is 1 (bit 0 of the Source Start Address
Register 0 is set), the first pixel of each line is in the high byte of the WORD and the contents of the
low byte are ignored. If the Source Phase is 0, the first pixel is in the low byte and the second pixel
is in the high byte. Depending on the Source Phase and the BitBLT Width, the last WORD may con-
tain only one pixel. In this case it is always in the low byte. The number of WORD writes the Bit-
BLT engine expects for 8 bpp color depths is shown in the following formula.
nWORDS = ((BitBLTWidth + 1 + SourcePhase)
÷ 2) × BitBLTHeight
Note: The BitBLT engine counts WORD writes in the BitBLT address space. This does not imply only 16-bit
CPU instructions are acceptable. If a system is able to separate one DWORD write into two WORD
writes and the CPU writes the low word before the high word, then 32-bit CPU instructions are ac-
ceptable. Otherwise, 16-bit CPU instructions are required.