參數(shù)資料
型號: M37733S4
廠商: Mitsubishi Electric Corporation
英文描述: 16-BIT CMOS MICROCOMPUTER
中文描述: 16位CMOS微機
文件頁數(shù): 16/35頁
文件大?。?/td> 726K
代理商: M37733S4
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16
MITSUBISHI MICROCOMPUTERS
M37733EHLXXXHP
PROM VERSION OF M37733MHLXXXHP
V
CC
= 5 V,
f(X
IN
) = 12 MHz (square waveform),
(f(f
2
) = 6 MHz),
f(X
CIN
) = 32.768 kHz,
in operating (Note 1)
V
CC
= 3 V,
f(X
IN
) = 12 MHz (square waveform),
(f(f
2
) = 6 MHz),
f(X
CIN
) = 32.768 kHz,
in operating (Note 1)
V
CC
= 3 V,
f(X
IN
) = 12 MHz (square waveform),
(f(f
2
) = 0.75 MHz),
f(X
CIN
) : Stopped,
in operating
V
CC
= 3 V,
f(X
IN
) = 12 MHz (square waveform),
f(X
CIN
) = 32.768 kHz,
when a WIT instruction is executed (Note 2)
V
CC
= 3 V,
f(X
IN
) : Stopped,
f(X
CIN
) = 32.768 kHz,
in operating (Note 3)
V
CC
= 3 V,
f(X
IN
) : Stopped,
f(X
CIN
) = 32.768 kHz,
when a WIT instruction is executed (Note 4)
Ta = 25 °C,
when clock is stopped
Ta = 85 °C,
when clock is stopped
mA
mA
mA
μ
A
μ
A
μ
A
μ
A
μ
A
Max.
9
6
0.8
12
60
6
1
20
Limits
Typ.
4.5
3
0.4
6
30
3
Unit
Min.
Test conditions
Symbol
Parameter
ELECTRICAL CHARACTERISTICS
(Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, unless otherwise noted)
When single-chip
mode, output pins
are open, and
other pins are V
SS
.
Power source
current
I
CC
Limits
Typ.
Min.
Max.
10
± 3
25
R
LADDER
t
CONV
V
REF
V
IA
Note.
This applies when the main clock division selection bit = “0” and f(f
2
) = 6 MHz.
Resolution
Absolute accuracy
Ladder resistance
Conversion time
Reference voltage
Analog input voltage
V
REF
= V
CC
V
REF
= V
CC
V
REF
= V
CC
Bits
LSB
k
s
V
V
10
19.6
2.7
V
CC
V
REF
0
Symbol
Parameter
Test conditions
Unit
A–D CONVERTER CHARACTERISTICS
(V
CC
= AV
CC
= 5 V, V
SS
= AV
SS
= 0 V, Ta = –40 to +85 °C, f(X
IN
) = 12 MHz, unless otherwise noted (Note))
Notes 1.
This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop
bit = “1”.
2.
This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.
3.
This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.
4.
This applies when the X
COUT
drivability selection bit = “0” and the system clock stop bit at wait state = “1”.
μ
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