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APPENDIX
Appendix 6. Machine instructions
7721 Group User’s Manual
17–42
ACC,C
←ACC+M+C
ACC
←ACC∧M
Symbol
Functions
Details
Adds the carry, the accumulator and the memory
contents.The result is entered into the accumulator. When
the D flag is “0,” binary additions is done, and when the
D flag is “1,” decimal addition is done.
Obtains the logical product of the contents of the accumu-
lator and the contents of the memory . The result is en-
tered into the accumulator.
Shifts the accumulator or the memory contents one bit to
the left. “0” is entered into bit 0 of the accumulator or the
memory. The contents of bit 15 ( bit 7 when the m flag is
“1”) of the accumulator or memory before shift is entered
into the C flag.
Tests the specified bit of the memory. Branches when all
the contents of the specified bit is “0.”
Tests the specified bit of the memory. Branches when all
the contents of the specified bit is “1.”
Branches when the contents of the C flag is “0.”
Branches when the contents of the C flag is “1.”
Branches when the contents of the Z flag is “1.”
Branches when the contents of the N flag is “1.”
Branches when the contents of the Z flag is “0.”
Branches when the contents of the N flag is “0.”
Jumps to the address indicated by the program counter
plus the offset value.
Executes software interruption.
Branches when the contents of the V flag is “0.”
Branches when the contents of the V flag is “1.”
Makes the contents of the specified bit in the memory “0.”
Makes the contents of the C flag “0.”
Makes the contents of the I flag “0.”
Specifies the bit position in the processor status register
by the bit pattern of the second byte in the instruction, and
sets “0” in that bit.
Makes the contents of the V flag “0.”
Compares the contents of the accumulator with the con-
tents of the memory.
Mb=0?
Mb=1?
C=0?
C=1?
Z=1?
N=1?
Z=0?
N=0?
PC
←PC±offset
PG
←PG+1
(when carry occurs)
PG
←PG–1
(when borrow occurs)
PC
←PC+2
M(S)
←PG
S
←S–1
M(S)
←PCH
S
←S–1
M(S)
←PCL
S
←S–1
M(S)
←PSH
S
←S–1
M(S)
←PSL
S
←S–1
I
←1
PCL
←ADL
PCH
←ADH
PG
←0016
V=0?
V=1?
C
←0
Mb
←0
Makes the contents of the m flag “0.”
I
←0
m
←0
PSb
←0
V
←0
ACC–M
IMP
IMM
A
DIR
DIR,b
DIR,X
DIR,Y
(DIR)
(DIR,X)
(DIR),Y
op
n
op
Addressing modes
AND
(Notes 1,2)
ADC
(Notes 1,2)
ASL
(Note 1)
BBC
(Notes 3,5)
BBS
(Notes 3,5)
BCC
(Note 3)
BCS
(Note 3)
BEQ
(Note 3)
BMI
(Note 3)
BNE
(Note 3)
BPL
(Note 3)
BRA
(Note 4)
BRK
BVC
(Note 3)
BVS
(Note 3)
CLB
(Note 5)
CLC
CLI
CLM
CLV
CMP
(Notes 1,2)
CLP
n
op n
58
D8
1
21
29
C2
22
2 61 72 71
2
3
42
75
3
42
72
3 42
61
3 42
71
10 3
2
35
32
2 21
31 82
43
3
42
32
3 42
21
3
4
1
2
72
16 72
3
4
2
4
D5
42
31
10
3
C1
D1
42
D1
8
10
2
3
42
C1
2
3
2
3
6
2
3
7
5
7
2
5
7
5
8
6
8
6
8
6
m=0
C
← b15 b0 ←0
m=1
C
← b7 b0 ←0
# op n# op n# op n#
69
2
65
2
4
42
69
43
42
65
6
75
72
#
op
op n# op
# op
#n #
#
8
9
22
25 47 2
42
29
3
42
25
6
42
35
93
0A 2
06
42
0A
00 15 2
14 8
18 2
2
B8
C9
42
C9
42
C5
4
C5
42
D5
42
D2
7
93
2
Appendix 6. Machine instructions