參數(shù)資料
型號: M37630E4T-XXXFS
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 34/48頁
文件大?。?/td> 563K
代理商: M37630E4T-XXXFS
MITSUBISHI
ELECTRIC
34
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 37
Structure of CAN mask and code registers
Fig. 38
Note 1:
Structure of CAN transmission and reception buffer registers
All CAN related SFRs must not be written in “CAN sleep” mode.
address
0033
16
7
Not used Not used Not used
0
CSID
10
CSID
9
CSID
8
CSID
7
CSID
6
CSID
5
CSID
4
CSID
3
CSID
2
CSID
1
CSID
0
Not used Not used
Not used Not used Not used Not used
CEID
17
CEID
16
CEID
15
CEID
14
CEID
13
CEID
12
CEID
11
CEID
10
CEID
9
CEID
8
CEID
7
CEID
6
CEID
5
CEID
4
CEID
3
CEID
2
CEID
1
CEID
0
Not used Not used
7
Not used Not used Not used MSID
10
0
MSID
9
MSID
8
MSID
7
MSID
6
MSID
5
MSID
4
MSID
3
MSID
2
MSID
1
MSID
0
Not used Not used
Not used Not used Not used Not used MEID
17
MEID
16
MEID
15
MEID
14
MEID
13
MEID
12
MEID
11
MEID
10
MEID
9
MEID
8
MEID
7
MEID
6
MEID
5
MEID
4
MEID
3
MEID
2
MEID
1
MEID
0
Not used Not used
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
Acceptance code
registers:
Acceptance mask
registers:
Select the bit pattern of identifiers which allows to pass acceptance filtering.
0 : Mask identifier bit (do not care)
1 : Compare identifier bit with acceptance code register bit
(Not used: write to “0”)
name
CAC0
CAC1
CAC2
CAC3
CAC4
CAM0
CAM1
CAM2
CAM3
CAM4
offset
0000
16
7
Not used Not used Not used
0
SID
10
SID
9
SID
8
SID
7
SID
6
SID
5
SID
4
SID
3
SID
2
SID
1
SID
0
RTR/SRR
IDE
Not used Not used Not used Not used
EID
17
EID
16
EID
15
EID
14
EID
13
EID
12
EID
11
EID
10
EID
9
EID
8
EID
7
EID
6
EID
5
EID
4
EID
3
EID
2
EID
1
EID
0
RTR
r1
0001
16
0002
16
0003
16
0004
16
Not used Not used Not used
r
0
DLC
3
DLC
2
DLC
1
DLC
0
0005
16
0006
16
data byte 0
0007
16
data byte 1
0008
16
data byte 2
0009
16
data byte 3
000A
16
data byte 4
000B
16
data byte 5
000C
16
data byte 6
000D
16
data byte 7
Calculate the actual address as follows:
TxD buffer address = 0040
16
+ offset
RxD buffer address = 0050
16
+offset
(Not used: write to “0”)
name
CTB0, CRB0
CTB1, CRB1
CTB2, CRB2
CTB3, CRB3
CTB4, CRB4
CTB5, CRB5
CTB6, CRB6
CTB7, CRB7
CTB8, CRB8
CTB9, CRB9
CTBA, CRBA
CTBB, CRBB
CTBC, CRBC
CTBD, CRBD
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