MITSUBISHI MICROCOMPUTERS
7630 Group
17
MITSUBISHI
ELECTRIC
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 15
Structure of interrupt request and control registers A, B and C
7
Interrupt request register A
(address 0002
16
)
IREQA
CAN wake up
interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
7
0
7
0
0 :
1 :
No interrupt request
Interrupt requested
0
Not used
(returns to ”0” when read)
External interrupt INT
0
request bit
External interrupt INT
1
request bit
CAN successful transmission
interrupt request bit
CAN successful receive
interrupt request bit
CAN overrun interrupt request bit
CAN error passive
interrupt request bit
CAN bus off interrupt request bit
Interrupt request register B
(address 0003
16
)
IREQB
Interrupt request register C
(address 0004
16
)
IREQC
UART receive complete
(receive buffer full)
interrupt request bit
UART transmit complete
(transmit register empty)
interrupt request bit
UART transmit buffer empty
interrupt request bit
UART receive error interrupt
request bit
Serial I/O interrupt request bit
AD conversion complete
interrupt request bit
Key-on wake-up interrupt request bit
Not used (returns to ”0” when read)
7
0
Not used (returns to ”0” when read)
External interrupt INT
0
enable bit
External interrupt INT
1
enable bit
CAN successful transmission
interrupt enable bit
CAN successful receive
interrupt enable bit
CAN overrun interrupt enable bit
CAN error passive
interrupt enable bit
CAN bus off interrupt enable bit
Interrupt control register A
(address 0005
16
)
ICONA
7
0 Interrupt control register B
(address 0006
16
)
ICONB
CAN wake–up interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
7
0
Interrupt control register C
(address 0007
16
)
ICONC
UART receive complete
(receive buffer full)
interrupt enable bit
UART transmit complete
(transmit register empty)
interrupt enable bit
UART transmit buffer empty
interrupt enable bit
UART receive error interrupt
enable bit
Serial I/O interrupt enable bit
AD conversion complete
interrupt enable bit
Key-on wake-up interrupt enable bit
Not used (returns to ”0” when read)
0:
1:
Interrupt disabled
Interrupt enabled