參數(shù)資料
型號： M37560MFA-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 64/71頁
文件大?。?/td> 993K
代理商： M37560MFA-XXXFP
Rev.1.02
Jul 31, 2003
page 67 of 69
7560 Group (A version)
Table 24 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Note: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note)
Serial I/O1 output valid time (Note)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
140
30
0.2 tC (SCLK2)
40
Symbol
Parameter
Limits
Min.
ns
Unit
tC (SCLK1)/2–30
–30
Typ.
Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
Table 25 Switching characteristics (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
ns
Unit
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
350
100
0.2 tC (SCLK2)
100
Symbol
Parameter
Limits
Min.
tC (SCLK1)/2–100
–30
Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
Typ.
tC (SCLK2)/2–160
0
tC (SCLK2)/2–240
0
Fig. 65 Circuit for measuring output switching characteristics
Measurement output pin
100 pF
CMOS output
Note: When P71–P77, P40 and bit 4 of the UART control
register (address 001B16) is “1” (N-channel open-
drain output mode).
N-channel open-drain output (Note)
1 k
100 pF
Measurement output pin
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