參數(shù)資料
型號(hào)： M37560M9-XXXGP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 26/65頁(yè)
文件大?。?/td> 955K
代理商： M37560M9-XXXGP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
26
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer mode
The timer counts f(X
IN
)/16 (or f(X
CIN
)/16 in low-speed mode).
(2) Period measurement mode
CNTR
1
interrupt request is generated at rising/falling edge of
CNTR
1
pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period measure-
ment mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR
1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR
1
pin input signal is found by
CNTR
1
interrupt. When using a timer in this mode, set the corre-
sponding port P5
5
direction register to input mode.
(3) Event counter mode
The timer counts signals input through the CNTR
1
pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P5
5
direction register to input mode.
(4) Pulse width HL continuously measure-
ment mode
CNTR
1
interrupt request is generated at both rising and falling
edges of CNTR
1
pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P5
5
direction register to input mode.
I
Note on CNTR
1
interrupt active edge selection
CNTR
1
interrupt active edge depends on the CNTR
1
active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR
1
interrupt request is generated at both rising and
falling edges of CNTR
1
pin input signal regardless of the setting of
CNTR
1
active edge switch bit.
Fig. 21 Structure of timer Y mode register
T
(
i
T
m
e
M
r
Y
:
m
d
o
d
d
r
e
e
s
s
r
e
0
g
0
i
s
2
t
8
1
e
r
Y
a
6
)
b
7
b
0
Not used (return
“
0
”
when read)
Timer Y operating mode bits
b5 b4
0
0 : Timer mode
0
1 : Period measurement mode
1
0 : Event counter mode
1
1 : Pulse width HL continuously
measurement mode
CNTR
1
active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Falling edge active for CNTR
1
interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR
1
interrupt
Timer Y stop control bit
0 : Count start
1 : Count stop
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