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參數(shù)資料
| 型號： | M37560M7-XXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | RES-ARRAY 39-OHM 4-ELEMENT 5% 0.063W CONVEX THK-FILM SMD-1206 TR-7-PA |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 27/65頁 |
| 文件大小： | 955K |
| 代理商： | M37560M7-XXXFP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
27
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an inadvert-
ent count down of the timer. Therefore, rewrite the value of timer
whenever the count source is changed.
G
Timer 2 Write Control
If the timer 2 write control bit is
“
0
”
, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is
“
1
”
, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
G
Timer 2 Output Control
When the timer 2 (T
OUT
) is output enabled, an inversion signal
from pin T
OUT
is output each time timer 2 underflows.
In this case, set the port P5
6
shared with the port T
OUT
to the out-
put mode.
I
Note on Timer 1 to Timer 3
When the count source of timers 1 to 3 is changed, the timer
counting value may be changed large because a thin pulse is gen-
erated in count input of timer. If timer 1 output is selected as the
count source of timer 2 or timer 3, when timer 1 is written, the
counting value of timer 2 or timer 3 may be changed large be-
cause a thin pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Fig. 22 Structure of timer 123 mode register
T
O
U
U
T
:
:
T
/
φ
:
T
O
:
T
O
m
e
0
:
1
:
i
m
e
0
:
1
:
o
u
t
a
t
a
o
t
r
r
p
t
t
u
T
/
φ
U
2
w
W
r
i
t
W
r
i
t
r
2
c
T
i
m
f
(
X
I
(
o
r
f
e
r
3
:
T
i
m
:
f
(
X
I
(
o
r
m
e
r
1
0
:
f
(
X
I
(
o
1
:
f
(
X
C
N
o
t
u
s
u
a
a
t
p
t
a
“
“
u
o
o
t
e
d
a
d
a
o
u
e
r
N
)
/
1
(
X
C
c
o
u
e
r
N
)
/
1
f
(
X
C
c
o
N
)
/
r
f
(
X
C
I
e
d
(
c
H
L
t
u
u
c
t
a
t
a
n
t
1
o
6
I
n
1
o
6
I
u
n
1
6
I
N
)
r
e
t
i
v
o
o
p
t
p
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i
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s
o
u
t
e
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e
t
t
p
r
o
d
e
r
o
l
a
n
l
u
r
p
u
d
p
u
l
i
n
l
t
c
t
c
c
e
t
g
u
t
b
s
a
b
h
h
e
t
s
w
i
t
c
h
b
i
t
0
1
S
S
t
t
”
”
u
u
t
t
t
t
T
O
c
t
n
u
u
n
n
i
b
b
i
t
s
e
t
0
1
i
U
a
l
e
e
d
d
T
/
φ
r
e
e
l
T
r
i
a
o
n
n
l
e
d
l
y
c
c
o
u
n
t
e
r
a
T
t
i
o
n
b
i
t
N
)
t
/
s
u
1
o
t
6
u
p
i
n
c
t
e
l
o
s
w
e
-
l
s
e
p
c
e
t
i
e
o
d
n
m
b
o
t
d
e
)
T
i
0
1
m
r
i
u
N
)
t
/
s
1
o
6
u
i
n
c
e
l
o
s
w
e
-
l
s
e
p
c
e
t
i
e
o
d
n
m
b
o
t
d
e
)
T
i
r
i
N
)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
T
(
i
T
m
e
2
r
3
M
1
2
3
:
a
d
m
d
o
r
d
e
e
s
r
e
0
g
0
i
2
s
t
e
r
6
)
1
s
9
1
Note:
Internal clock
φ
is f(X
CIN
)/2 in the low-speed mode.
b
7
b
0
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