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| 型號： | M37546G2-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 8.90 X 28 MM, 1.78 MM PITCH, PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 105/105頁 |
| 文件大?。?/td> | 1105K |
| 代理商： | M37546G2-XXXSP |
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REJ03B0160-0122 Rev.1.22 Mar 13, 2009
page 97 of 100
7546 Group
3. Notes common to clock synchronous serial I/O and UART
(1) Set the serial I/Oi (i=1, 2) control register again after the trans-
mission and the reception circuits are reset by clearing both
the transmit enable bit and the receive enable bit to “0.”
Fig. 6 Sequence of setting serial I/Oi control register again
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of the
serial I/Oi control register
Set both the transmit enable bit (TE)
and the receive enable bit (RE), or
one of them to “1”
(2) The transmit shift completion flag changes from “1” to “0” with
a delay of 0.5 to 1.5 shift clocks. When data transmission is
controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(3) When data transmission is executed at the state that an exter-
nal clock input is selected as the synchronous clock, set “1” to
the transmit enable bit while the SCLKi is “H” state. Also, write
to the transmit buffer register while the SCLKi is “H” state.
(4) When the transmit interrupt is used, set as the following se-
quence.
Serial I/Oi transmit interrupt enable bit is set to “0” (disabled).
Serial I/Oi transmit enable bit is set to “1”.
Serial I/Oi transmit interrupt request bit is set to “0” after 1 or
more instructions have been executed.
Serial I/Oi transmit interrupt enable bit is set to “1” (enabled).
<Reason>
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and transmit shift completion flag are set to “1”.
Accordingly, even if the timing when any of the above flags is set
to “1” is selected for the transmit interrupt source, interrupt request
occurs and the transmit interrupt request bit is set.
(5) Write to the baud rate generator (BRGi) while the transmit/re-
ceive operation is stopped.
Can be set
with the LDM
instruction at
the same time
Notes on Serial I/O1
1. I/O pin function when serial I/O1 is enabled.
The pin functions of P12/SCLK1 and P13/SRDY1 are switched to as
follows according to the setting values of a serial I/O1 mode selec-
tion bit (bit 6 of serial I/O1 control register (address 001A16)) and
a serial I/O1 synchronous clock selection bit (bit 1 of serial I/O1
control register).
(1) Serial I/O1 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY1 output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY1 output pin.
(2) Serial I/O1 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it
functions P13 pin. It can be used as a normal I/O pin.
Note on Bus Collision Detection
When serial I/O1 is operating at half-duplex communication, set
bus collision detection interrupt to be disabled.
Notes on Serial I/O2
1. I/O pin function when serial I/O2 is enabled
The pin functions of P06/SCLK2 and P07/SRDY2 are switched to as
follows according to the setting values of a serial I/O2 mode selec-
tion bit (bit 6 of serial I/O2 control register (address 003016)) and a
serial I/O2 synchronous clock selection bit (bit 2 of serial I/O2 con-
trol register).
(1) Serial I/O2 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O2 synchronous clock selection bit
“0” : P06 pin turns into an output pin of a synchronous clock.
“1” : P06 pin turns into an input pin of a synchronous clock.
Setup of a SRDY2 output enable bit (SRDY)
“0” : P07 pin can be used as a normal I/O pin.
“1” : P07 pin turns into a SRDY2 output pin.
(2) Serial I/O2 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O2 synchronous clock selection bit
“0”: P06 pin can be used as a normal I/O pin.
“1”: P06 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it
functions P07 pin. It can be used as a normal I/O pin.
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