參數(shù)資料
型號(hào): M37542M2V-XXXGP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁(yè)數(shù): 34/139頁(yè)
文件大小: 1448K
代理商: M37542M2V-XXXGP
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)當(dāng)前第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)
7542 Group
Rev.3.02
Oct 31, 2006
Page 129 of 134
REJ03B0006-0302
Notes on Output Compare
1. When the selected source timer of each compare channel is
stopped, written data to compare register is loaded to the com-
pare latch simultaneously.
2. Do not write the same data to both of compare latch x0 (x=0, 1,
2, 3) and x1.
3. When setting value of the compare register is larger than timer
setting value, compare match signal is not generated. Accord-
ingly, the output waveform is fixed to “L” or “H” level.
However, when setting value of another compare register is
smaller than timer setting value, this compare match signal is
generated. Accordingly, if the corresponding compare latch y
(y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to “1”
(valid), compare match interrupt request occurs.
4. When the compare x trigger enable bit is cleared to “0” (dis-
abled), the match trigger to the waveform output circuit is
disabled. Accordingly, the output waveform can be fixed to “L”
or “H” level.
However, in this case, the compare match signal is generated.
Accordingly, if the corresponding compare latch y (y=00, 01, 10,
11, 20, 21, 30, 31) interrupt source bit is set to “1”
(valid),compare match interrupt request occurs.
Notes on Input Capture
1. If the capture trigger is input while the capture register (low-or-
der and high-order) is in read, captured value is changed
between high-order reading and low-order reading. Accordingly,
some countermeasure by software is recommended, for ex-
ample comparing the values that twice of read.
2. Timer A cannot be used for the capture source timer in the fol-
lowing state;
XIN oscillation selected by clock division ratio selection bits
(bits 7 and 6 of CPU mode register (address 3B16))
Timer A count source: On-chip oscillator output.
Timer B cannot be used for the capture source timer in the fol-
lowing state;
XIN oscillation selected by clock division ratio selection bits
Timer B count source: Timer A underflow
Timer A count source: On-chip oscillator output.
3. As shown below, when the capture input is performed to both
capture latch 00 and 01 at the same time, the value of capture
0 status bit (bit 4 of capture/compare status register (address
2216)) is undefined (same as capture 1).
When “1” is written to capture latch 00 software trigger bit (bit 0
of capture software trigger register (address 1316)) and capture
latch 01 software trigger bit (bit 1 of capture software trigger reg-
ister) at the same time
When external trigger of capture latch 00 and software trigger of
capture latch 01 occur at the same time
When external trigger of capture latch 01 and software trigger of
capture latch 00 occur at the same time
4. When the capture interrupt is used as the interrupt for return
from stop mode, set the capture 0 noise filter clock selection
bits (bits 5 and 4 of capture mode register (address 2016)) to
“00 (Filter stop)” (same as capture 1).
相關(guān)PDF資料
PDF描述
M37542M2-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
M37542F8SP 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
M37542F8FP 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO36
M37542F8GP 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32
M37542F4GP 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M37542M2-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37542M2-XXXGP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37542M2-XXXHP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37542M2-XXXSP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37542M4-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER