參數(shù)資料
型號(hào): M37542M2T-XXXGP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁(yè)數(shù): 40/139頁(yè)
文件大?。?/td> 1448K
代理商: M37542M2T-XXXGP
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)當(dāng)前第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)
7542 Group
Rev.3.02
Oct 31, 2006
Page 134 of 134
REJ03B0006-0302
Notes on On-chip Oscillation Division Ratio
When the clock division ratio is switched from f(XIN) to on-chip
oscillator by the clock division ratio selection bits (bits 7 and 6 of
CPU mode register (address 3B16)), the on-chip oscillator divi-
sion ratio (bits 1 and 0 of on-chip oscillation division ratio
selection register (address 3716)) is “102” (on-chip oscillator
middle-speed mode (ROSC/8)).
Notes on Oscillation Stop Detection Circuit
1. After the reset by the oscillation stop detection, the value of fol-
lowing bits are retained, not initialized.
Ceramic or RC oscillation stop detection function active bit
Bit 1 of MISRG (address 3B16)
Oscillation stop detection status bit
Bit 3 of MISRG
2. Oscillation stop detection status bit is initialized (“0”) by the fol-
lowing operation.
External reset
Write “0” data to the ceramic or RC oscillation stop detection
function active bit.
3. The oscillation stop detection circuit is not included in the emu-
lator MCU “M37542RSS”.
Notes on CPU Rewrite Mode
Take the notes described below when rewriting the flash memory
in CPU rewrite mode.
1. Operation speed
During CPU rewrite mode, set the system clock φ to 4.0 MHz or
less using the clock division ratio selection bits (bits 6 and 7 of
CPU mode register).
2. Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode.
3. Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
4. Watchdog timer
If the watchdog timer has been already activated, internal reset
due to an underflow will not occur because the watchdog timer is
surely initialized during program or erase.
5. Reset
Reset is always valid. The MCU is activated using the boot mode
at release of reset in the condition of CNVss = “H”, so that the pro-
gram will begin at the address which is stored in addresses
FFFC16 and FFFD16 of the boot ROM area.
Electric Characteristic Differences Between
Mask ROM, Flash Memory MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation among mask ROM and flash
memory version MCUs due to the differences in the manufacturing
processes.
When manufacturing an application system with the flash memory
and then switching to use of the mask ROM version, perform suffi-
cient evaluations for the commercial samples of the mask ROM
version.
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ce-
ramic capacitor of 0.01 F to 0.1 F is recommended.
相關(guān)PDF資料
PDF描述
M37542F8VGP 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32
M37542M2V-XXXGP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32
M37542M2V-XXXGP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32
M37542M2-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
M37542F8SP 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M37542M2-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37542M2-XXXGP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37542M2-XXXHP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37542M2-XXXSP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37542M4-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER