- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45035 > M37542M2-XXXFP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO36 PDF資料下載
參數(shù)資料
| 型號： | M37542M2-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO36 |
| 封裝： | 8.4 X 15 MM, 0.80 MM PITCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 44/122頁 |
| 文件大小： | 1311K |
| 代理商： | M37542M2-XXXFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁
7542 Group
Rev.3.03
Jul 11, 2008
Page 28 of 117
REJ03B0006-0303
Interrupt Request Generation, Acceptance, and Handling
Interrupts have the following three phases.
(i) Interrupt Request Generation
An interrupt request is generated by an interrupt source (ex-
ternal interrupt signal input, timer underflow, etc.) and the
corresponding request bit is set to “1”.
(ii) Interrupt Request Acceptance
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance con-
ditions (interrupt request bit, interrupt enable bit, and interrupt
disable flag) and interrupt priority levels for accepting interrupt
requests. When two or more interrupt requests are generated
simultaneously, the highest priority interrupt is accepted. The
value of the interrupt request bit for an unaccepted interrupt
remains the same and acceptance is determined at the next
interrupt acceptance timing point.
(iii) Handling of Accepted Interrupt Request
The accepted interrupt request is processed.
Figure 25 shows the time up to execution in the interrupt process-
ing routine, and Figure 26 shows the interrupt sequence.
Figure 27 shows the timing of interrupt request generation, inter-
rupt request bit, and interrupt request acceptance.
Interrupt Handling Execution
When interrupt handling is executed, the following operations are
performed automatically.
(1) Once the currently executing instruction is completed, an in-
terrupt request is accepted.
(2) The contents of the program counters and the processor sta-
tus register at this point are pushed onto the stack area in
order from 1 to 3.
1.High-order bits of program counter (PCH)
2.Low-order bits of program counter (PCL)
3.Processor status register (PS)
(3) Concurrently with the push operation, the jump address of the
corresponding interrupt (the start address of the interrupt pro-
cessing routine) is transferred from the interrupt vector to the
program counter.
(4) The interrupt request bit for the corresponding interrupt is set
to “0”. Also, the interrupt disable flag is set to “1” and multiple
interrupts are disabled.
(5) The interrupt routine is executed.
(6) When the RTI instruction is executed, the contents of the reg-
isters pushed onto the stack area are popped off in the order
from 3 to 1. Then, the routine that was before running interrupt
processing resumes.
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each inter-
rupt to execute the interrupt processing routine.
■ Notes on Interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
When switching external interrupt active edge
Related registers:
Interrupt edge selection register (address 003A16)
Timer X mode register (address 002B16)
Capture mode register (address 002016)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit (active edge switch bit, trigger
mode bit).
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
Main routine
Interrupt handling
routine
Interrupt request
generated
Interrupt request
acceptance
Interrupt routine
starts
Interrupt sequence
7 cycles
0 to 16* cycles
7 to 23 cycles
* When executing DIV instruction
Stack push
Vector fetch
Fig. 25 Time up to execution in interrupt routine
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37542M2-XXXHP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQCC36 |
| M37542M2-XXXGP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32 |
| M37542F4SP | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32 |
| M37542F8HP | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQCC36 |
| M37544G2ASP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37542M2-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37542M2-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37542M2-XXXSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37542M4-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37542M4-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。