參數(shù)資料
型號： M37542F8VFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO36
封裝： 8.4 X 15 MM, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁數(shù)： 113/139頁
文件大?。?/td> 1448K
代理商： M37542F8VFP
7542 Group
Rev.3.02
Oct 31, 2006
Page 75 of 134
REJ03B0006-0302
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: Effective only when the suspend enable bit = “1”.
b7
b0
Erase Suspend enble bit (Notes 1)
0 : Suspend invalid
1 : Suspend valid
Erase Suspend
request bit (Notes 2)
0 : Erase restart
1 : Suspend request
Erase Suspend flag
0 :
Erase active
1 :
Erase inactive (Erase Suspend mode)
Not used (do not write “1” to this bit.)
Flash memory control register 1
(FMCR1: address : 0FE116: initial value: 4016)
Figure 96 shows the flash memory control register 1.
Bit 0 of the flash memory control register 1 is the Erase suspend
enable bit. By setting this bit to “1”, the erase suspend mode to
suspend erase processing temporarily when block erase com-
mand is executed can be used. In order to set this bit to “1”,
writing “0” and “1” in succession to bit 0. In order to set this bit to
“0”, write “0” only to bit 0.
Bit 1 of the flash memory control register 1 is the erase suspend
request bit. By setting this bit to “1” when erase suspend enable
bit is “1”, the erase processing is suspended.
Bit 6 of the flash memory control register 1 is the erase suspend
flag. This bit is cleared to “0” at the flash erasing.
Figure 97 shows the flash memory control register 2.
Bit 0 of the flash memory control register 1 is the all user block E/
W enable bit. By setting this bit to “0”, Erase/Write to all user block
(blocks 0, 1, 2) is disabled. As a result, error writing in program to
write only to data block can be prevented.
Fig. 96 Structure of flash memory control register 1
Fig. 97 Structure of flash memory control register 2
Table 10 Erase/Write disable setting
CPU rewrite
mode select bit
0
1
All user block
E/W enable bit
0
1
0
1
8KB user block
E/W enable bit
0
1
0
1
0
1
0
1
Block 0: 8KB
Block 1: 8KB
E/W disabled (RESET)
E/W disabled
E/W enabled
Block 2: 16KB
E/W disabled (RESET)
E/W disabled
E/W enabled
Data block A: 2KB
Data block B: 2KB
E/W disabled (RESET)
E/W disabled
E/W enabled
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: Effective only when the CPU rewrite mode select bit = “1”.
b7
b0
Reserved bit (returns “1” when read)
Reserved bits (do not write “1” to this bit.)
All user block E/W enable
bit (Notes 1, 2)
0 : E/W disabled
1 : E/W enabled
Not used (do not write “1” to this bit.)
Flash memory control register 2
(FMCR2: address : 0FE216: initial value: 0116)
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