參數(shù)資料
型號(hào)： M37534E4FP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 30/55頁
文件大小： 610K
代理商： M37534E4FP
7534 Group
Rev.2.00 Jun 21, 2004 page 30 of 54
REJ03B0099-0200Z
G
Serial I/O2
The serial I/O2 function can be used only for clock synchronous se-
rial I/O.
For clock synchronous serial I/O2 the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8 bits which control various
serial I/O functions.
For receiving, set “0” to bit 3.
When receiving, bit 7 is cleared by writing dummy data to serial I/
O2 register after shift is completed.
Bit 7 is set earlier a half cycle of shift clock than completion of shift
operation. Accordingly, when checking shift completion by using
this bit, the setting is as follows:
(1) check that this bit is set to “1”,
(2) wait a half cycle of shift clock,
(3) read/write to serial I/O2 register.
Fig. 32 Structure of serial I/O2 control registers
Fig. 33 Block diagram of serial I/O2
Serial I/O2 control register
(SIO2CON: address 0030
16
)
S
DATA
pin selection bit (Note)
0 : I/O port/S
DATA
input
1 : S
DATA
output
Not used
(returns “0” when read)
Internal synchronous clock selection bits
000 : f(X
IN
)/8
001 : f(X
IN
)/16
010 : f(X
IN
)/32
011 : f(X
IN
)/64
110 : f(X
IN
)/128
111 : f(X
IN
)/256
b7 b0
Transfer direction selection bit
0 : LSB first
1 : MSB first
S
CLK
pin selection bit
0 : External clock (S
CLK
is an input)
1 : Internal clock (S
CLK
is an output)
Transmit / receive shift completion flag
0 : shift in progress
1 : shift completed
Note :
When using it as an S
DATA
input, set the port P1
3
direction register to “0”.
“1”
“0”
“0”
“1”
“0”
“1”
1/8
1/16
1/32
1/64
1/128
1/256
X
IN
Data bus
Serial I/O2
interrupt request
S
DATA
pin selection bit
Serial I/O counter 2 (3)
Serial I/O shift register 2 (8)
S
CLK
pin selection bit
Internal synchronous
clock selection bits
D
P1
2
/S
CLK
P1
3
/S
DATA
P1
2
latch
S
CLK pin
selection bit
S
CLK
P1
3
latch
S
DATA
pin selection bit
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