- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370845 > M37516M6-A46HP (Mitsubishi Electric Corporation) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PDF資料下載
參數(shù)資料
| 型號(hào)： | M37516M6-A46HP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 26/54頁 |
| 文件大?。?/td> | 358K |
| 代理商： | M37516M6-A46HP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
26/54
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
GE
Table 5 Set values of I
2
C clock control register and SCL
frequency
Setting value of
CCR4–CCR0
Standard clock
CCR4
CCR3
CCR2
CCR1
CCR0
Fig. 25 Structure of I
2
C clock control register
SCL frequency
(at
φ
= 4 MHz, unit : kHz)
mode
Setting disabled
Setting disabled
Setting disabled
–
(Note 2)
–
(Note 2)
High-speed clock
mode
Setting disabled
Setting disabled
Setting disabled
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
34.5
33.3
32.3
100
83.3
333
250
400
(Note 3)
166
[I
2
C Clock Control Register (S2)] 002F
16
The I
2
C clock control register (address 002F
16
) is used to set ACK
control, SCL mode and SCL frequency.
Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 5.
Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the
standard clock mode is selected. When the bit is set to “1,” the
high-speed clock mode is selected.
When connecting the bus of the high-speed mode I
2
C bus stan-
dard (maximum 400 kbits/s), use 8 MHz or more oscillation
frequency f(X
IN
) and 2 division clock.
Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock
8
is generated.
When this bit is set to “0,” the ACK return mode is selected and
SDA goes to “L” at the occurrence of an ACK clock. When the bit
is set to “1,” the ACK non-return mode is selected. The SDA is
held in the “H” status at the occurrence of an ACK clock.
However, when the slave address agree with the address data in
the reception of address data at ACK BIT = “0,” the SDA is auto-
matically made “L” (ACK is returned). If there is a disagreement
between the slave address and the address data, the SDA is auto-
matically made “H” (ACK is not returned).
8
ACK clock: Clock for acknowledgment
Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an ac-
knowledgment response of data transfer. When this bit is set to
“0,” the no ACK clock mode is selected. In this case, no ACK clock
occurs after data transmission. When the bit is set to “1,” the ACK
clock mode is selected and the master generates an ACK clock
each completion of each 1-byte data transfer. The device for
transmitting address data and control data releases the SDA at
the occurrence of an ACK clock (makes SDA “H”) and receives the
ACK bit generated by the data receiving device.
Note:
Do not write data into the I
2
C clock control register during transfer. If
data is written during transfer, the I
2
C clock generator is reset, so
that data cannot be transferred normally.
500/CCR value
(Note 3)
17.2
16.6
16.1
1000/CCR value
(Note 3)
Notes 1:
Duty of SCL clock output is 50 %. The duty becomes 35 to 45 %
only when the high-speed clock mode is selected and CCR value
= 5 (400 kHz, at
φ
= 4 MHz). “H” duration of the clock fluctuates
from –4 to +2 machine cycles in the standard clock mode, and
fluctuates from –2 to +2 machine cycles in the high-speed clock
mode. In the case of negative fluctuation, the frequency does not
increase because “L” duration is extended instead of “H” duration
reduction.
These are value when SCL clock synchronization by the syn-
chronous function is not performed. CCR value is the decimal
notation value of the SCL frequency control bits CCR4 to CCR0.
2:
Each value of SCL
frequency exceeds the limit at
φ
= 4 MHz or
more. When using these setting value, use
φ
of 4 MHz or less.
3:
The data formula of SCL frequency is described below:
φ
/(8
CCR value) Standard clock mode
φ
/(4
CCR value) High-speed clock mode (CCR value
≠
5)
φ
/(2
CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of
φ
frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the SCL frequency by
setting the SCL frequency control bits CCR4 to CCR0.
ACK
ACK
BIT
FAST
MODE
CCR4 CCR3 CCR2 CCR1 CCR0
I
2
C clock control register
(S2 : address 002F
16
)
b7
b0
SCL frequency control bits
Refer to Table 5.
SCL mode specification bit
0 : Standard clock mode
1 : High-speed clock mode
ACK bit
0 : ACK is returned.
1 : ACK is not returned.
ACK clock bit
0 : No ACK clock
1 : ACK clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37516M6-A48KP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37516M6-A70HP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37516M6-A71HP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37516M6 | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37516RSS | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37516M6-A48KP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37516M6-A70HP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37516M6-A71HP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37516M6H-XXXKP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37516M6-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。