7480 Group and 7481 Group User's Manual
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1.14 Serial I/O
HARDWARE
Stopping Transmission/Reception of Clock Synchronous Serial I/O
In order to stop the transmit operation in half-duplex transmission, clear the transmit enable bit of
the serial I/O control register to ‘0’. As a result, the following stop and initialization of transmit
operation are performed:
To stop and initialize the clock supplied to the transmit shift register
To clear the transmit shift register (Only when ‘0’ is written to the transmit enable bit while the
SCLK pin input is HIGH, selecting an external clock as the synchronous clock.)
To clear the transmit buffer empty flag and transmit shift completion flag
REASON: Neither stopping transmit operation nor initializing the transmitter circuit is performed
even when the serial I/O enable bit is cleared to ‘0’ (serial I/O disabled), and internal
transmit operation continues. (Because serial I/O pins TxD, RxD, SCLK, and SRDY
function as I/O port pins, transmit data cannot be output to the external.)
In order to stop the receive operation in half-duplex transmission, clear the receive enable bit or
the serial I/O enable bit of the serial I/O control register to ‘0’. As a result, the following stop and
initialization of the receive operation are performed:
To stop and initialize the clock supplied to the receive shift register
To clear the receive shift register
To clear every error flag
To clear the receive buffer full flag
In order to stop the transmit and receive operations in full-duplex transmission, clear both the
transmit enable bit and the receive enable bit of the serial I/O control register to ‘0’ at the same
time. (To stop only one of the transmit or receive operation cannot be done in the full-duplex
communication of clock synchronous serial I/O.)
REASON: In clock synchronous serial I/O, the same clock is used for transmission and reception.
Therefore, transmission and reception cannot be synchronized when either transmit or
receive operation is disabled, causing displacement of bit positions.
Re-setting Serial I/O Control Register
Re-set the serial I/O control register according to the following sequence:
Clear both the transmit and receive enable bits of the serial I/O control register to ‘0’ to stop and
initialize transmit and receive operations.
Set bits 0 to 3 and 6 of the serial I/O control register.
Set the transmit enable bit or receive enable bit to ‘1’.
(Procedures and can be performed simultaneously with the LDM instruction.)