參數(shù)資料
型號: M37481E8SS
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 35/97頁
文件大?。?/td> 1076K
代理商: M37481E8SS
35
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A transmit data collision is detected between LSB and MSB of
transmit data in the clock synchronous serial I/O mode or between
the start bit and stop bit of transmit data in the UART mode. Bus
collision detection can be performed by both the internal clock and
the external clock.
A block diagram is shown in Figure 34. A timing diagram is shown
in Figure 35. A bus collision detection control register is shown in
Figure 36.
Fig. 34 Block diagram of bus arbitration interrupt circuit
Fig. 36 Structure of bus collision detection control register
T
X
D
R
X
D
Shift clock
D
Q
Bus arbitration interrupt
request
Bus collision detection
enable bit
TE
Transmit shift clock
Transmit pin TxD
Receive pin RxD
Bus arbitration interrup
t
generation
Data collision
Bus Collision Detection
The 7480/7481 group can detect a bus collision by setting the bus
collision detection enable bit to “1”.
When transmission is started in the clock synchronous or asyn-
chronous (UART) serial I/O mode, the transmit pin TxD is
compared with the receive pin RxD in synchronization with a rising
edge of transmit shift clock. If they do not coincide with each other,
a bus arbitration interrupt request occurs (bus collision detection).
Fig. 35 Timing diagram of bus arbitration interrupt
b7
b0
Bus collision detection control register
(BUSARBCON address 00E5
16
)
Bus collision detection enable bit
0 : Collision detection disabled
1 : Collision detection enabled
Not used (“0” at read)
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