參數(shù)資料
型號(hào)： M37481E8SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 31/97頁(yè)
文件大小： 1076K
代理商： M37481E8SP
31
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
the serial I/O mode selection bit of the serial I/O control register
(address 00E2
16
) to “1”.
In the clock synchronous serial I/O, the transmitter-side microcom-
puter and the receiver-side microcomputer must use the same
clock for serial I/O operation. If an internal clock is used as oper-
ating clock, a transfer is started by a write signal to the transmit/
receive buffer register.
Fig. 28 Block diagram of clock synchronous serial I/O
Fig. 29 Operation of clock synchronous serial I/O function
Data bus
Data bus
Receive buffer register
Clock control circuit
Serial I/O control register
Falling edge
detection
Serial I/O status register
F/F
1/4
1/4
1/4
Transmit shift register shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Serial I/O synchronous
clock selection
bit (SCS)
Frequency division
ratio 1/(n+1)
Baud rate generator
P1
6
P1
4
Shift clock
P1
5
P1
7
Clock control
circuit
Receive shift register
Transmit shift register
Transmit buffer register
T
X
D
S
RDY
S
CLK
R
X
D
X
IN
S
RDY
output enable
bit (SRDY)
Address 00E0
16
Address 00E2
16
Address 00E0
16
Address 00E1
16
Address 00E4
16
BRG count source
selection bit (CSS)
Transmit interrupt source
selection bit (TIC)
Transmit enable
bit (TE)
Receive
enable bit
(RE)
Serial I/O enable bit
(SIOE)
Serial I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation when serial I/O is in opera-
tion.
(1) Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode can be selected by setting
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE) detection
Transmit/receive shift clock,
1/8 – 1/8192 of internal clock, or
external clock
Serial output TxD
Serial input RxD
Receive enable signal S
RDY
Write signal to receive/
transmit buffer register
(address 00E0
16
)
Notes 1 : The transmit interrupt (TI) can be selected to be generated either when the transmit buffer is empty (TBE = 1) or after the
transmit shift operation is completed (TSC = 1) by using the transmit interrupt source selection bit (TIC) of the serial I/O control
register.
2 : If data is written to the transmit buffer register when TSC = 0, the transmit clock is generated continuously, and serial data is
output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
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