參數(shù)資料
型號: M37480MX
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 24/97頁
文件大?。?/td> 1076K
代理商: M37480MX
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
24
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 17 Block diagram of timer X and timer Y
PWM generating circuit
D
T
Q
Programmable one-shot
output circuit
T
Q
Q
S
Programmable waveform
generation mode
Pulse output
mode
CNTR
0
edge
selection bit
“1”
“0”
Programmable
one-shot
output mode
PWM mode
CNTR
0
edge
selection bit
“0”
Timer X (low-order) latch Timer X (high-order) latch
Timer X (high-order)
Timer X (low-order)
Edge detecting circuit
Timer X stop control bit
Timer X count source
selection bit
Pulse width measurement mode
Pulse cycle measurement mode
CNTR
0
edge
selection bit
“001”
“100”
“101”
“110”
Timer X
operating mode bits
Programmable one-shot
output mode
PWM mode
Output level latch
P3
0
/INT
0
P4
0
/CNTR
0
P4
0
direction
register
P4
0
latch
f(X
IN
)/2
f(X
IN
)/8
f(X
IN
)/16
“1”
“1”
“0”
INT
0
interrupt
request
Timer X
interrupt request
Pulse output mode
D
T
Q
Programmable one-shot
output circuit
T
Q
Q
S
Programmable waveform
generation mode
Pulse output
mode
CNTR
1
edge
selection bit
“1”
“0”
Programmable
one-shot
output mode
PWM mode
CNTR
1
edge
selection bit
“0”
Edge detecting circuit
Timer Y count source
selection bit
“001”
“100”
“101”
“110”
Timer Y
operating mode bits
Programmable one-shot
output mode
PWM mode
Output level latch
P3
1
/INT
1
P4
1
/CNTR
1
P4
1
direction
register
P4
1
latch
f(X
IN
)/2
f(X
IN
)/8
f(X
IN
)/16
“1”
Pulse output mode
Data bus
“1”
“0”
Programmable waveform generation mode
Timer X trigger selection bit
Timer Y stop control bit
D
T
Q
“1”
“0”
Programmable waveform generation mode
Timer Y trigger selection bit
CNTR
1
edge
selection bit
“1”
“0”
“1”
INT
0
edge sele“0”
“1”
INT
1
edge sele“0”
Pulse width measurement mode
Pulse cycle measurement mode
PWM generating circuit
Timer Y (low-order) latch Timer Y (high-order) latch
Timer Y (high-order)
Timer Y (low-order)
CNTR
0
interrupt
request
INT
1
interrupt
request
Timer Y
interrupt request
CNTR
1
interrupt
request
D
T
Q
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